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Re: [Qemu-arm] [Qemu-devel] [PATCH 22/23] target-arm: Enable EL2 feature
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH 22/23] target-arm: Enable EL2 feature bit on A53 and A57 |
Date: |
Tue, 20 Dec 2016 13:32:35 +0000 |
On 19 December 2016 at 22:04, Alistair Francis <address@hidden> wrote:
> On Tue, Dec 13, 2016 at 8:11 AM, Edgar E. Iglesias
> <address@hidden> wrote:
>> On Tue, Dec 13, 2016 at 10:36:23AM +0000, Peter Maydell wrote:
>>> Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and
>>> Cortex-A57, since this is all now sufficiently implemented
>>> to work with the GICv3. We provide the usual CPU property
>>> to disable it for backwards compatibility with the older
>>> virt boards.
>>>
>>> In this commit, we disable the EL2 feature on the
>>> virt and ZynpMP boards, so there is no overall effect.
>>> Another commit will expose a board-level property to
>>> allow the user to enable EL2.
>>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>>> index 0d86ba3..bc4e66b 100644
>>> --- a/hw/arm/xlnx-zynqmp.c
>>> +++ b/hw/arm/xlnx-zynqmp.c
>>> @@ -258,6 +258,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
>>> **errp)
>>>
>>> object_property_set_bool(OBJECT(&s->apu_cpu[i]),
>>> s->secure, "has_el3", NULL);
>>> + object_property_set_bool(OBJECT(&s->apu_cpu[i]),
>>> + false, "has_el2", NULL);
>
> Hey Peter,
>
> We would like this to be settable. I think just copying the s->secure
> (same as EL3) should be fine here.
>
> Let me know what is easier for you, if you want to just add an extra
> patch to enable it or if you want me to send a patch doing it?
I'm not really set up to test the xilinx boards, so I'd rather
let you test and send the extra patch to enable it for them.
thanks
-- PMM
- [Qemu-arm] [PATCH 03/23] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU, (continued)
- [Qemu-arm] [PATCH 03/23] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 01/23] target-arm: Log AArch64 exception returns, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 18/23] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 12/23] target-arm: Add ARMCPU fields for GIC CPU i/f config, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 22/23] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 20/23] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs, Peter Maydell, 2016/12/13
- Re: [Qemu-arm] [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs, Andrew Jones, 2016/12/13
- Re: [Qemu-arm] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs, Andrew Jones, 2016/12/16
- Re: [Qemu-arm] [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs, Alistair Francis, 2016/12/19