question make document sec "3.8 Overriding Part of Another Makefile"

[loody]

dear all:
I read the 3.8 section of make document and I type the command below
on my linux machine:

foo:
        ls -lt
%: force
        @$(MAKE) -f Makefile $@
force: ;

The result is look like:
address@hidden make]# make foo
make[1]: Entering directory `/root/make'
make[2]: Entering directory `/root/make'
make[3]: Entering directory `/root/make'
make[4]: Entering directory `/root/make'
......

The make call itself recursively.
Below are my assumptions about this problem.
1. the prereq of foo is empty, so it go to target: %: force
2. since  target force is an empty command, it finally execute "
@$(MAKE) -f Makefile $@"
Are above assumptions correct?

Meanwhile, I do some experiment as:
foo:
        ls -lt
%:
        @$(MAKE) -f Makefile $@
force: ;

The make will execute "ls -lt".
I read the document sec5.9 and it says empty command is used for
preventing  a target from getting implicit commands.
why is it so important to the pattern rule above?
appreciate your help,
miloody