Re: how to properly define a make file that builds two distinct objects

[Paul Smith]

On Mon, 2008-05-19 at 09:52 -0400, Robert P. J. Day wrote:

>   TARGETLIB = fubar.so
>   SRCS = src1.c src2.c snafu.c
> 
>   include sharedlib.mk

>   obviously, i can do the same to build an executable, or a loadable
> module, etc, etc.  but what if the "building" of that directory
> should result in a multitude of final objects -- say, an executable, a
> shared library *and* two loadable modules?

>   are there other approaches that people use?  i'm just interested in
> "best practices" here.  thanks.

The best practice I've seen used everywhere (and what I use personally)
is to conditionalize all the variables with the target names.  So, you
can do something like:

        TARGETLIB = fubar.so barfoo.so

        fobar.so_SRCS = src1.c src2.c

        barfoo.so_SRCS = src3.cpp src4.c

etc.  Now in your rules to build things, conditionalize all the
variables with $@ like this:

        $(CC) ... $(address@hidden)

anyway, you get the idea.  Sometimes it's better to use $* instead; it
really depends on what you're doing.

When you really get going you can even do things like:

        fubar.so_CFLAGS = -Werror
        src1_CFLAGS = -Wno-error

or whatever, to have custom flags on a per-target basis.

This way you can mix and match as many different targets, and different
KINDS of targets, all in the same makefile.  And, it's 100% descriptive
(in most cases) with only variable settings and no rules necessary (in
the individual makefiles).

-- 
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