Re: Executing a shell script in a Makefile

[Paul D. Smith]

%% G2345C <address@hidden> writes:

  g> all ::
  g>         if [ -r $(GPS_ENGINE_MANIFEST) ] ; then \
  g>            cd $(BUILD_DIR) && $(SHELL) ./copfile.sh ;
  g> \
  g>         fi 
  g>         cd $(GPS_ENGINE_OBJS_DIR) && \
  g>            $(LIBTOOL) $(LIBTOOL_LINK_TAG) $(GCC) -o
  g> libtest.la \
  g>               $(wildcard $(GPS_ENGINE_OBJS_DIR)/*.lo)
  g> -rpath $(INSTALL_LIB_DIR) ; \
  g>         else \
  g>          .....
  g>         fi

  g> the $(wildcard $(GPS_ENGINE_OBJS_DIR)/*.lo) is not
  g> expended properly... it's empty the first time i ran,
  g> but it i run the make file the second time it expend
  g> all the .lo files properly ... what cause this
  g> problem?

That's a MAKE function.  That means make expands the function based on
its internal understanding of what's in the directory _BEFORE_ it
invokes the shell script.

So any files that are added to the directory during the running of the
shell script are not used here, because make has replaced that
invocation with static values before starting your script.

Again if you look at the output make prints you'll see what the wildcard
function is expanding to.


Since you're in a shell already you don't need $(wildcard ...); the
shell will do it for you.  Just use:

              $(GPS_ENGINE_OBJS_DIR)/*.lo -rpath ...

directly.

-- 
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 Paul D. Smith <address@hidden>          Find some GNU make tips at:
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 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist