Static Pattern use of function in Prereq

[Jaye Speaks]

Makefile question:

got a folder structure:
/
Makefile
        /src
                page1.htmlpp
                page2.htmlpp
                page3.htmlpp
        /_CUST1
        /_CUST2
        /_CUST3
        /_CUST4
        
trying to build a Makefile that will run each src/*.htmlpp through
cpp to preprocess ifdefs resulting in customer version of .html pages
and have these .html pages created in the appropriate customer
version directory.

My questions are related to implementing the targets and prereqs
somewhat dynamically.  My current design is to utilize Static Pattern
rules to generate the prereqs, but it looks like you can't utilize
text transformation functions in the prereq pattern.  I maybe headed
in the wrong direction and something more recursive is the proper
implementation.

I need help figuring out two things.

1. Is there a way to modify the prereq in a Static Pattern using text
functions.  If not, what is another solution.

2. What are some acceptable ways to pass multiple variables to a
rule.  In my makefile below, is parse up the target variable to
determine its path and reuse that as a value I need in the command. 
Doesn't seem like the best implementation.
        
Any tips or suggestions would be appreciated.

#====== MAKEFILE =======
PPFLAGS = -P
PP = cpp $(PPFLAGS)

BUILDS := _CUST1 _CUST2 _CUST3 _CUST4
SRCDIR := src

SRCDIRFILES := $(wildcard $(SRCDIR)/*.htmlpp)
EXTCHNG := $(patsubst %.htmlpp,%.html,$(SRCDIRFILES))
OUTFILES := $(foreach BUILD,$(BUILDS),$(subst $(SRCDIR), $(BUILD),
$(EXTCHNG)))

.PHONY : all
all : $(OUTFILES)

$(OUTFILES) : %.html : $(subst $(SRCDIR), $(BUILD), %.htmlpp)  # <- -
- - THE USE OF FUNCTION HERE DOESN'T WORK
    $(PP) -D$(subst /,,$(dir $@)) $< > $@

.PHONY : dump
dump :
    @echo '$(OUTFILES)'

.PHONY : clean $(BUILDS)
clean : $(BUILDS)
$(BUILDS):
    -rm -rf $@/*


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