Re: [Gnucap-devel] language plugin help

[al davis]

On Sunday 15 April 2012, John Griessen wrote:
> On 04/15/2012 01:28 PM, address@hidden wrote:
> > 2. Pin names are "\2" and "\1".  They should be "p" and
> > "n".
> 
> For many passive parts the symbol libraries are not
> polarized, so some kind of text processing of the netlist
> would be helpful, and it should be open and pointed out to
> the user so they aren't confused by its action.  For a
> resistor or nonpolarized capacitor model, either way will be
> fine and better than doing nothing.

Regardless, there is a standard that should be followed.  I 
didn't create the standard.  Admittedly, I am refering to the 
Verilog-AMS standard, version 2.3, section E.4, page 367, table 
E.1.  This section defines interface to standard Spice 
components.  There may be others.

So, comparing "p" and "n" to "n" and "p", I agree that in many 
cases there is no difference.  But, if you probe the voltage or 
current in the device, reversing "n" and "p" reverses the 
reading.

But "\2" and "\1" ... where is the standard for that?

Given that a lot of imports are non-standard, we do need a way 
to deal with it, other than to just say "you are wrong".

It can't be built-in.  It really needs to be some kind of 
"include".

Maybe even ...

module RESISTOR (\2, \1);
  parameter real r;
  resistor #(.r(r)) R1 (\2, \1);
endmodule

This isn't the permanent answer because it adds another level of 
indirection, but maybe it will provide some insight.

Some work on the geda side is really needed anyway ..  The geda 
spice netlister has specific code for every device.  Mostly the 
spice netlister uses a single attribute "VALUE" to send a string 
to spice.  There, you just give it the whole string.

The netlister needs to handle general attributes, to pass them 
on with appropriate syntax .. spice syntax for spice, verilog 
syntax for verilog, and so on.