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Re: [Gnucap-devel] language plugin help
From: |
Felix Salfelder |
Subject: |
Re: [Gnucap-devel] language plugin help |
Date: |
Sun, 15 Apr 2012 16:43:11 +0200 |
User-agent: |
Mutt/1.5.20 (2009-06-14) |
Hi John.
On Sun, Apr 15, 2012 at 09:11:53AM -0500, John Griessen wrote:
> I'm wanting to make translation from gschem netlists work as a simulatable
> verilog-a netlist for gnucap. I'm new to C++, have done some C programs.
>
> Should I just wait some more until this dust settles, or is it OK
> to bug you with C++ newbie questions about how to understand gnucap language
> plugins?
>
> My goals could support Savant's "A plugin to translate a schematic
> file into a netlist preserving the placement of components in form
> of comments which can be parsed and re-translated into the original
> schematic".
in fact i think Savants work makes a gschem->verilog-a-netlist
conversion tool quite obsolete. with the spice language plugin, you can
convert a netlist to verilog:
gnucap> spice
gnucap-spice>R1 1 2 3
gnucap-spice>.verilog
gnucap-verilog>list
resistor #(.r( 3.)) R1 (.p(1),.n(2));
now the geda plugin does what you intend, doesn't it?
> and might be necessary for his plan to work,
I don't see this yet.
> since when I've tried
> using verilog-a gnetlist output with gnucap in the past, I only got
> partial functioning.
thats interesting. if the verilog language plugin is incomplete (and i
guess it is), lets fix it! can you post an example?
regards
felix