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[Commit-gnuradio] r8991 - usrp2/trunk/firmware/lib
From: |
eb |
Subject: |
[Commit-gnuradio] r8991 - usrp2/trunk/firmware/lib |
Date: |
Wed, 23 Jul 2008 19:06:27 -0600 (MDT) |
Author: eb
Date: 2008-07-23 19:06:27 -0600 (Wed, 23 Jul 2008)
New Revision: 8991
Modified:
usrp2/trunk/firmware/lib/Makefile.am
usrp2/trunk/firmware/lib/db_rfx.c
usrp2/trunk/firmware/lib/u2_init.c
Log:
split clock functions out from u2_init
Modified: usrp2/trunk/firmware/lib/Makefile.am
===================================================================
--- usrp2/trunk/firmware/lib/Makefile.am 2008-07-24 00:08:08 UTC (rev
8990)
+++ usrp2/trunk/firmware/lib/Makefile.am 2008-07-24 01:06:27 UTC (rev
8991)
@@ -20,10 +20,12 @@
noinst_LIBRARIES = \
libu2fw.a
+
libu2fw_a_SOURCES = \
ad9510.c \
ad9777.c \
buffer_pool.c \
+ clocks.c \
db_basic.c \
db_init.c \
db_rfx.c \
@@ -48,3 +50,35 @@
printf.c \
spi.c \
u2_init.c
+
+
+noinst_HEADERS = \
+ ad9510.h \
+ ad9777.h \
+ ad9777_regs.h \
+ bool.h \
+ buffer_pool.h \
+ clocks.h \
+ db.h \
+ db_base.h \
+ dbsm.h \
+ eth_mac.h \
+ eth_mac_regs.h \
+ eth_phy.h \
+ ethernet.h \
+ hal_io.h \
+ hal_uart.h \
+ i2c.h \
+ lsadc.h \
+ lsdac.h \
+ mdelay.h \
+ memcpy_wa.h \
+ memory_map.h \
+ memset_wa.h \
+ nonstdio.h \
+ pic.h \
+ print_rmon_regs.h \
+ spi.h \
+ stdint.h \
+ stdio.h \
+ u2_init.h
Modified: usrp2/trunk/firmware/lib/db_rfx.c
===================================================================
--- usrp2/trunk/firmware/lib/db_rfx.c 2008-07-24 00:08:08 UTC (rev 8990)
+++ usrp2/trunk/firmware/lib/db_rfx.c 2008-07-24 01:06:27 UTC (rev 8991)
@@ -23,7 +23,9 @@
#include <stdio.h>
#include <mdelay.h>
#include <lsdac.h>
+#include <clocks.h>
+
bool rfx_init_rx(struct db_base *db);
bool rfx_init_tx(struct db_base *db);
bool rfx_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
@@ -443,23 +445,19 @@
bool
rfx_init_tx(struct db_base *dbb)
{
- struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
- ad9510_write_reg(0x42, 0x08); // enable output 6 (db_tx_clk), CMOS
- ad9510_write_reg(0x55, 0x80); // Bypass Div #6, 100 MHz clock
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ //struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
+ clocks_enable_tx_dboard(true, 0);
return true;
}
bool
rfx_init_rx(struct db_base *dbb)
{
- struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
- ad9510_write_reg(0x43, 0x08); // enable output 7 (db_rx_clk), CMOS
- ad9510_write_reg(0x57, 0x80); // Bypass Div #7, 100 MHz clock
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ //struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
+ clocks_enable_rx_dboard(true, 0);
// test gain
- db->base.set_gain(db,U2_DOUBLE_TO_FXPT_GAIN(45.0));
+ dbb->set_gain(dbb,U2_DOUBLE_TO_FXPT_GAIN(45.0));
printf("set the gain\n");
return true;
}
@@ -551,6 +549,8 @@
{
struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
+ // FIXME
+
return false;
}
Modified: usrp2/trunk/firmware/lib/u2_init.c
===================================================================
--- usrp2/trunk/firmware/lib/u2_init.c 2008-07-24 00:08:08 UTC (rev 8990)
+++ usrp2/trunk/firmware/lib/u2_init.c 2008-07-24 01:06:27 UTC (rev 8991)
@@ -28,7 +28,7 @@
#include "bool.h"
#include "mdelay.h"
#include "ad9777.h"
-#include "ad9510.h"
+#include "clocks.h"
#include "db.h"
//#include "nonstdio.h"
@@ -52,122 +52,9 @@
// init spi, so that we can switch over to the high-speed clock
spi_init();
- // Set up basic clocking functions in AD9510
- ad9510_write_reg(0x45, 0x00); // CLK2 drives distribution
- ad9510_write_reg(0x3D, 0x00); // Turn on output 1 (FPGA CLK), normal levels
- ad9510_write_reg(0x4B, 0x80); // Bypass divider 1
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ // set up the default clocks
+ clocks_init();
- spi_wait();
-
- // Set up PLL for 10 MHz reference
- // Reg 4, A counter, Don't Care
- ad9510_write_reg(0x05, 0x00); // Reg 5, B counter MSBs, 0
- ad9510_write_reg(0x06, 0x05); // Reg 6, B counter LSBs, 5
- // Reg 7, Loss of reference detect, doesn't work yet, 0
-
-#define LOCK_TO_EXT_REF 0
-#define LOCK_TO_MIMO_REF 0
-#define LOCK_NONE 1
-#define THEY_LOCK_TO_ME 0
-
- timesync_regs->tick_control = 4;
-
- // if(I WANT TO LOCK TO A REFERENCE CLOCK)
- if(LOCK_TO_EXT_REF || LOCK_TO_MIMO_REF) {
- // Reg 8, Charge pump on, dig lock det, positive PFD, 47
- ad9510_write_reg(0x08, 0x47);
- }
- else {
- // Reg 8, Charge pump off, dig lock det, positive PFD
- ad9510_write_reg(0x08, 0x00);
- }
-
- // Reg 9, Charge pump current, 0x40=3mA, 0x00=650uA
- ad9510_write_reg(0x09, 0x00);
- // Reg A, Prescaler of 2, everything normal 04
- ad9510_write_reg(0x0A, 0x04);
- // Reg B, R Div MSBs, 0
- ad9510_write_reg(0x0B, 0x00);
- // Reg C, R Div LSBs, 1
- ad9510_write_reg(0x0C, 0x01);
- // Reg D, Antibacklash, Digital lock det, 0
-
- ad9510_write_reg(0x5A, 0x01); // Update Regs
-
- spi_wait();
-
- // Allow for clock switchover
- if (LOCK_NONE) {
- // Disable both ext clk inputs
- output_regs->clk_ctrl = 0x10;
- }
- else if (LOCK_TO_EXT_REF) {
- // turn on ref output and choose the SMA
- output_regs->clk_ctrl = 0x1C;
- }
- else if (LOCK_TO_MIMO_REF) {
- // Turn on ref output and choose the MIMO connector
- output_regs->clk_ctrl = 0x15;
- }
-
-#define TEST_CLK 1
-#define REV2 1
-#define HACKED 0
-
- // Set up other clocks
- if(TEST_CLK) {
- ad9510_write_reg(0x3C, 0x08); // Turn on output 0 -- Test output
- ad9510_write_reg(0x49, 0x80); // Bypass divider 0
- } else {
- ad9510_write_reg(0x3C, 0x02); // Turn off output 0
- }
-
- if (THEY_LOCK_TO_ME) {
- ad9510_write_reg(0x3E, 0x00); // Turn on output 2 (clk_exp_out), normal
levels
- ad9510_write_reg(0x4D, 0x00); // Turn on Div2
- ad9510_write_reg(0x4C, 0x44); // Set Div2 = 10, output a 10 MHz clock
- }
- else {
- ad9510_write_reg(0x3E, 0x02); // Turn off output 2 (clk_exp_out)
- ad9510_write_reg(0x4D, 0x80); // Bypass divider 2
- }
-
- if(HACKED) { // Using the indirect ETH Clk
- ad9510_write_reg(0x41, 0x02); // Turn on output 5, LVDS
- ad9510_write_reg(0x52, 0x11); // Div by 4
- ad9510_write_reg(0x53, 0x0);
- }
- else if (REV2) {
- ad9510_write_reg(0x41, 0x01); // Turn off output 5 (phy_clk)
- ad9510_write_reg(0x53, 0x80); // Bypass divider
- }
- else {
- ad9510_write_reg(0x40, 0x01); // Turn off output 4 (phy_clk)
- ad9510_write_reg(0x51, 0x80); // Bypass divider
- }
-
- ad9510_write_reg(0x42, 0x01); // Turn off output 6 (db_tx_clk)
- ad9510_write_reg(0x43, 0x01); // Turn off output 7 (db_rx_clk)
- ad9510_write_reg(0x5A, 0x01); // Update Regs
-
- // Enable ADCs
- output_regs->adc_ctrl = ADC_CTRL_ON;
-
- // Enable clock to ADCs and DACs
- ad9510_write_reg(0x3F, 0x00); // Turn on output 3 (DAC CLK), normal levels
- ad9510_write_reg(0x4F, 0x80); // Bypass Div #3
- if (REV2) {
- //ad9510_write_reg(0x40, 0x08); // Turn on out 4 (ADC clk), CMOS
- ad9510_write_reg(0x40, 0x02); // Turn on out 4 (ADC clk), LVDS
- ad9510_write_reg(0x51, 0x80); // Bypass Div #4
- } else {
- ad9510_write_reg(0x41, 0x08); // Turn on out 5 (ADC clk), CMOS
- ad9510_write_reg(0x53, 0x80); // Bypass Div #5
- }
-
- ad9510_write_reg(0x5A, 0x01); // Update Regs
-
// Set up AD9777 DAC
ad9777_write_reg(0, R0_1R);
ad9777_write_reg(1, R1_INTERP_4X | R1_REAL_MIX);
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