[Commit-gnuradio] r8461 - usrp2/trunk/fpga/opencores/aemb/rtl/verilog

[matt]

Author: matt
Date: 2008-05-20 12:13:16 -0600 (Tue, 20 May 2008)
New Revision: 8461

Modified:
   usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v
Log:
shawn fixed some MSR stuff plus the subtract bug differently than we did


Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v     2008-05-20 
18:11:58 UTC (rev 8460)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v     2008-05-20 
18:13:16 UTC (rev 8461)
@@ -1,4 +1,4 @@
-/* $Id: aeMB_xecu.v,v 1.10 2007/12/25 22:15:09 sybreon Exp $
+/* $Id: aeMB_xecu.v,v 1.12 2008/05/11 13:48:46 sybreon Exp $
 **
 ** AEMB MAIN EXECUTION ALU
 ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -90,34 +90,27 @@
      endcase // case (rMXTGT)
 
    // --- ADD/SUB SELECTOR ----
-   // FIXME: Redesign
-   // TODO: Refactor
-   // TODO: Verify signed compare
- 
-   wire            wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
-   wire [31:0]             wADD, wSUB, wRES_A, wCMP, wOPX;
+
+   reg                     rRES_ADDC;
+   reg [31:0]      rRES_ADD;
    
-   wire            wCMPU = (rOPA > rOPB);         
-   wire            wCMPF = (rIMM[1]) ? wCMPU :
-                           ((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] & 
~rOPA[31]));
+   wire [31:0]                 wADD;
+   wire                wADC;
+
+   wire                fCCC = !rOPC[5] & rOPC[1]; // & !rOPC[4]
+   wire                fSUB = !rOPC[5] & rOPC[0]; // & !rOPC[4]
+   wire                fCMP = !rOPC[3] & rIMM[1]; // unsigned only
+   wire                wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust
    
-   assign          {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};  
-   assign          wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
-   assign          wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & 
(!rOPC[5] & ~&rOPC[5:4]);
+   wire [31:0]                 wOPA = (fSUB) ? ~rOPA : rOPA;
+   wire                wOPC = (fCCC) ? rMSR_C : fSUB;
    
-   assign          {wSUBC,wSUB} = {wADDC,wADD}; 
-   assign          {wADDC,wADD} = (rOPB + wOPX) + wOPC; 
-      
-   reg                     rRES_ADDC;
-   reg [31:0]      rRES_ADD;
-   always @(rIMM or rOPC or wADD or wADDC or wCMP
-           or wCMPC or wSUB or wSUBC)
-     case ({rOPC[3],rOPC[0],rIMM[0]})
-       4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {wSUBC,wSUB}; // SUB
-       4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
-       default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};       
-     endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
+   assign              {wADC, wADD} = (rOPB + wOPA) + wOPC; // add carry
    
+   always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin
+      {rRES_ADDC, rRES_ADD} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry
+   end
+   
    // --- LOGIC SELECTOR --------------------------------------
 
    reg [31:0]      rRES_LOG;
@@ -255,7 +248,7 @@
    // --- MSR REGISTER -----------------
    
    // C
-   wire           fMTS = (rOPC == 6'o45) & rIMM[14];
+   wire           fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP;
    wire           fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
    
    always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
@@ -272,11 +265,11 @@
         3'o4: xMSR_C <= rMSR_C;         
         3'o5: xMSR_C <= rMSR_C;         
         default: xMSR_C <= 1'hX;       
-       endcase
+       endcase // case (rMXALU)
 
    // IE/BIP/BE
-   wire            fRTID = (rOPC == 6'o55) & rRD[0];   
-   wire            fRTBD = (rOPC == 6'o55) & rRD[1];
+   wire            fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP;   
+   wire            fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP;
    wire            fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
    wire            fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
    
@@ -361,7 +354,7 @@
        rMSR_IE <= 1'h0;
        rRESULT <= 32'h0;
        // End of automatics
-     end else if (gena) begin
+     end else if (gena) begin // if (grst)
        rRESULT <= #1 xRESULT;
        rDWBSEL <= #1 xDWBSEL;
        rMSR_C <= #1 xMSR_C;
@@ -375,6 +368,13 @@
 
 /*
  $Log: aeMB_xecu.v,v $
+ Revision 1.12  2008/05/11 13:48:46  sybreon
+ Backported Adder from AEMB2_EDK62.
+ Fixes 64-bit math problem reported by M. Ettus.
+
+ Revision 1.11  2008/01/19 15:57:36  sybreon
+ Fix MTS during interrupt vectoring bug (reported by M. Ettus).
+
  Revision 1.10  2007/12/25 22:15:09  sybreon
  Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
 
@@ -409,4 +409,4 @@
  Fixed various minor data hazard bugs.
  Code compatible with -O0/1/2/3/s generated code.
 
-*/
+*/
\ No newline at end of file