[Commit-gnuradio] r8460 - usrp2/trunk/fpga/opencores/aemb/rtl/verilog

[matt]

Author: matt
Date: 2008-05-20 12:11:58 -0600 (Tue, 20 May 2008)
New Revision: 8460

Modified:
   usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
Log:
supposedly fixes our interrupt problems


Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v     2008-05-20 
17:46:47 UTC (rev 8459)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v     2008-05-20 
18:11:58 UTC (rev 8460)
@@ -1,4 +1,4 @@
-/* $Id: aeMB_ibuf.v,v 1.9 2008/01/19 16:01:22 sybreon Exp $
+/* $Id: aeMB_ibuf.v,v 1.10 2008/01/21 01:02:26 sybreon Exp $
 **
 ** AEMB INSTRUCTION BUFFER
 ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -89,9 +89,14 @@
        rDINT <= 2'h0;
        rFINT <= 1'h0;
        // End of automatics
-     end else if (rMSR_IE) begin
-       rDINT <= #1 {rDINT[0], sys_int_i};      
-       rFINT <= #1 (wIREG == wINTOP) ? 1'b0 : (rFINT | wSHOT);
+     end else begin
+       if (rMSR_IE)
+         rDINT <= #1 
+                  {rDINT[0], sys_int_i};
+       
+       rFINT <= #1 
+                //(wIREG == wINTOP) ? 1'b0 : 
+                (rFINT | wSHOT) & rMSR_IE;
      end
 
    wire        fIMM = (rOPC == 6'o54);
@@ -151,6 +156,9 @@
 
 /*
  $Log: aeMB_ibuf.v,v $
+ Revision 1.10  2008/01/21 01:02:26  sybreon
+ Patch interrupt bug.
+
  Revision 1.9  2008/01/19 16:01:22  sybreon
  Patched problem where memory access followed by dual cycle instructions were 
not stalling correctly (submitted by M. Ettus)