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[Commit-gnuradio] r7817 - in gnuradio/branches/releases/3.1: . config gr
|
From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r7817 - in gnuradio/branches/releases/3.1: . config gr-gpio gr-gpio/src gr-gpio/src/fpga gr-gpio/src/fpga/include gr-gpio/src/fpga/lib gr-gpio/src/fpga/top gr-gpio/src/lib gr-gpio/src/python |
|
Date: |
Sun, 24 Feb 2008 12:07:54 -0700 (MST) |
Author: jcorgan
Date: 2008-02-24 12:07:53 -0700 (Sun, 24 Feb 2008)
New Revision: 7817
Added:
gnuradio/branches/releases/3.1/config/grc_gr_gpio.m4
gnuradio/branches/releases/3.1/gr-gpio/
gnuradio/branches/releases/3.1/gr-gpio/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/
gnuradio/branches/releases/3.1/gr-gpio/src/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_bottom.vh
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/gpio_input.v
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/io_pins.v
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/rx_chain_dig.v
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/tx_chain_dig.v
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/config.vh
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.csf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.esf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.psf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qpf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qsf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.rbf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.v
gnuradio/branches/releases/3.1/gr-gpio/src/lib/
gnuradio/branches/releases/3.1/gr-gpio/src/lib/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio.i
gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.cc
gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.h
gnuradio/branches/releases/3.1/gr-gpio/src/python/
gnuradio/branches/releases/3.1/gr-gpio/src/python/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/python/__init__.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_rx_sfile.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_fft.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_siggen.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/qa_gpio.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/run_tests.in
Removed:
gnuradio/branches/releases/3.1/gr-gpio/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/
gnuradio/branches/releases/3.1/gr-gpio/src/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_bottom.vh
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/gpio_input.v
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/io_pins.v
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/rx_chain_dig.v
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/tx_chain_dig.v
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/config.vh
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.csf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.esf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.psf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qpf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qsf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.rbf
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.v
gnuradio/branches/releases/3.1/gr-gpio/src/lib/
gnuradio/branches/releases/3.1/gr-gpio/src/lib/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio.i
gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.cc
gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.h
gnuradio/branches/releases/3.1/gr-gpio/src/python/
gnuradio/branches/releases/3.1/gr-gpio/src/python/Makefile.am
gnuradio/branches/releases/3.1/gr-gpio/src/python/__init__.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_rx_sfile.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_fft.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_siggen.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/qa_gpio.py
gnuradio/branches/releases/3.1/gr-gpio/src/python/run_tests.in
Modified:
gnuradio/branches/releases/3.1/config/Makefile.am
gnuradio/branches/releases/3.1/configure.ac
Log:
Applied changesets r7718 and r7740 on trunk to release branch.
Modified: gnuradio/branches/releases/3.1/config/Makefile.am
===================================================================
--- gnuradio/branches/releases/3.1/config/Makefile.am 2008-02-24 19:06:59 UTC
(rev 7816)
+++ gnuradio/branches/releases/3.1/config/Makefile.am 2008-02-24 19:07:53 UTC
(rev 7817)
@@ -41,6 +41,7 @@
grc_gr_audio_portaudio.m4 \
grc_gr_audio_windows.m4 \
grc_gr_comedi.m4 \
+ grc_gr_gpio.m4 \
grc_gr_gsm_fr_vocoder.m4 \
grc_gr_radar_mono.m4 \
grc_gr_radio_astronomy.m4 \
Copied: gnuradio/branches/releases/3.1/config/grc_gr_gpio.m4 (from rev 7618,
gnuradio/trunk/config/grc_gr_gpio.m4)
===================================================================
--- gnuradio/branches/releases/3.1/config/grc_gr_gpio.m4
(rev 0)
+++ gnuradio/branches/releases/3.1/config/grc_gr_gpio.m4 2008-02-24
19:07:53 UTC (rev 7817)
@@ -0,0 +1,49 @@
+dnl Copyright 2007,2008 Free Software Foundation, Inc.
+dnl
+dnl This file is part of GNU Radio
+dnl
+dnl GNU Radio is free software; you can redistribute it and/or modify
+dnl it under the terms of the GNU General Public License as published by
+dnl the Free Software Foundation; either version 3, or (at your option)
+dnl any later version.
+dnl
+dnl GNU Radio is distributed in the hope that it will be useful,
+dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
+dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+dnl GNU General Public License for more details.
+dnl
+dnl You should have received a copy of the GNU General Public License
+dnl along with GNU Radio; see the file COPYING. If not, write to
+dnl the Free Software Foundation, Inc., 51 Franklin Street,
+dnl Boston, MA 02110-1301, USA.
+
+AC_DEFUN([GRC_GR_GPIO],[
+ GRC_ENABLE([gr-gpio])
+
+ AC_CONFIG_FILES([ \
+ gr-gpio/Makefile \
+ gr-gpio/src/Makefile \
+ gr-gpio/src/fpga/Makefile \
+ gr-gpio/src/fpga/include/Makefile \
+ gr-gpio/src/fpga/top/Makefile \
+ gr-gpio/src/fpga/lib/Makefile \
+ gr-gpio/src/lib/Makefile \
+ gr-gpio/src/python/Makefile \
+ gr-gpio/src/python/run_tests
+ ])
+
+ passed=yes
+ # Don't do gr-gpio if usrp skipped
+ for dir in $skipped_dirs
+ do
+ if test x$dir = xusrp; then
+ AC_MSG_RESULT([Component gr-gpio requires usrp, which is not being
built.])
+ passed=no
+ fi
+ done
+
+ GRC_BUILD_CONDITIONAL([gr-gpio],[
+ dnl run_tests is created from run_tests.in. Make it executable.
+ AC_CONFIG_COMMANDS([run_tests_gpio], [chmod +x
gr-gpio/src/python/run_tests])
+ ])
+])
Modified: gnuradio/branches/releases/3.1/configure.ac
===================================================================
--- gnuradio/branches/releases/3.1/configure.ac 2008-02-24 19:06:59 UTC (rev
7816)
+++ gnuradio/branches/releases/3.1/configure.ac 2008-02-24 19:07:53 UTC (rev
7817)
@@ -215,6 +215,7 @@
GRC_GR_AUDIO_WINDOWS
GRC_GR_ATSC
GRC_GR_COMEDI
+GRC_GR_GPIO
GRC_GR_GSM_FR_VOCODER
GRC_GR_PAGER
GRC_GR_RADAR_MONO
Copied: gnuradio/branches/releases/3.1/gr-gpio (from rev 7618,
gnuradio/trunk/gr-gpio)
Property changes on: gnuradio/branches/releases/3.1/gr-gpio
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
Deleted: gnuradio/branches/releases/3.1/gr-gpio/Makefile.am
Copied: gnuradio/branches/releases/3.1/gr-gpio/Makefile.am (from rev 7618,
gnuradio/trunk/gr-gpio/Makefile.am)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/Makefile.am
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/Makefile.am 2008-02-24 19:07:53 UTC
(rev 7817)
@@ -0,0 +1,24 @@
+#
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+include $(top_srcdir)/Makefile.common
+
+SUBDIRS = src
Copied: gnuradio/branches/releases/3.1/gr-gpio/src (from rev 7618,
gnuradio/trunk/gr-gpio/src)
Property changes on: gnuradio/branches/releases/3.1/gr-gpio/src
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/Makefile.am
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/Makefile.am (from rev 7618,
gnuradio/trunk/gr-gpio/src/Makefile.am)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/Makefile.am
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/Makefile.am 2008-02-24
19:07:53 UTC (rev 7817)
@@ -0,0 +1,22 @@
+#
+# Copyright 2007 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+SUBDIRS = lib python fpga
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga (from rev 7618,
gnuradio/trunk/gr-gpio/src/fpga)
Property changes on: gnuradio/branches/releases/3.1/gr-gpio/src/fpga
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/Makefile.am
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/Makefile.am (from rev
7618, gnuradio/trunk/gr-gpio/src/fpga/Makefile.am)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/Makefile.am
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/Makefile.am 2008-02-24
19:07:53 UTC (rev 7817)
@@ -0,0 +1,22 @@
+#
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+SUBDIRS = include lib top
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include (from rev 7618,
gnuradio/trunk/gr-gpio/src/fpga/include)
Property changes on: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/Makefile.am
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/Makefile.am
(from rev 7618, gnuradio/trunk/gr-gpio/src/fpga/include/Makefile.am)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/Makefile.am
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/Makefile.am
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,24 @@
+#
+# Copyright 2007 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+EXTRA_DIST = \
+ common_config_2rxhb_2txdig.vh \
+ common_config_bottom.vh
Deleted:
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh
Copied:
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh
(from rev 7618,
gnuradio/trunk/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh)
===================================================================
---
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh
(rev 0)
+++
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,71 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006,2007 Matt Ettus
+// Copyright (C) 2008 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+ `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_SINGLE and TX_DUAL are currently valid]
+//`define TX_SINGLE
+ `define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// If TX_DIG_ON is defined each transmit channel sends its I lsb and Q lsb to
gpio pins
+// The lsb bits of the analog output signal are truncated
+ `define TX_DIG_ON
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* receive circuitry built
+ `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+//`define RX_SINGLE
+ `define RX_DUAL
+//`define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+ `define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+ `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+ `define RX_CIC_ON
+
+// ------------------------------------------------------------
+// If RX_DIG_ON is defined each receive channel sends has its I lsb and Q lsb
replaced by digital input from gpio pins
+// So the analog signals are truncated to 15 bits
+ `define RX_DIG_ON
Deleted:
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_bottom.vh
Copied:
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_bottom.vh
(from rev 7618, gnuradio/trunk/gr-gpio/src/fpga/include/common_config_bottom.vh)
===================================================================
---
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_bottom.vh
(rev 0)
+++
gnuradio/branches/releases/3.1/gr-gpio/src/fpga/include/common_config_bottom.vh
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,133 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006,2007 Matt Ettus
+// Copyright (C) 2008 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+// ====================================================================
+// This is the common tail for standard configuation
+// ====================================================================
+//
+// >>>> DO NOT EDIT BELOW HERE <<<<
+//
+// N.B., *all* the remainder of the code should be conditionalized
+// only in terms of:
+//
+// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB,
+// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB,
+// RX_NCO_ON, RX_CIC_ON
+// ====================================================================
+
+`ifdef TX_ON
+
+ `ifdef TX_SINGLE
+ `define TX_EN_0
+ `ifdef TX_DIG_ON
+ `define TX_EN_DIG_0
+ `define TX_CAP_DIG 1
+ `endif
+ `define TX_CAP_NCHAN 3'd1
+ `endif
+
+ `ifdef TX_DUAL
+ `define TX_EN_0
+ `define TX_EN_1
+ `define TX_CAP_NCHAN 3'd2
+ `ifdef TX_DIG_ON
+ `define TX_EN_DIG_0
+ `define TX_EN_DIG_1
+ `define TX_CAP_DIG 1
+ `endif
+ `endif
+
+ `ifdef TX_QUAD
+ `define TX_EN_0
+ `define TX_EN_1
+ `define TX_EN_2
+ `define TX_EN_3
+ `ifdef TX_DIG_ON
+ `define TX_EN_DIG_0
+ `define TX_EN_DIG_1
+ `define TX_CAP_DIG 1
+ `endif
+ `define TX_CAP_NCHAN 3'd4
+ `endif
+
+ `ifdef TX_HB_ON
+ `define TX_CAP_HB 1
+ `else
+ `define TX_CAP_HB 0
+ `endif
+
+`else // !ifdef TX_ON
+
+ `define TX_CAP_NCHAN 3'd0
+ `define TX_CAP_HB 0
+
+`endif // !ifdef TX_ON
+
+// --------------------------------------------------------------------
+
+`ifdef RX_ON
+
+ `ifdef RX_SINGLE
+ `define RX_EN_0
+ `define RX_CAP_NCHAN 3'd1
+ `ifdef RX_DIG_ON
+ `define RX_EN_DIG_0
+ `define RX_CAP_DIG 1
+ `endif
+ `endif
+
+ `ifdef RX_DUAL
+ `define RX_EN_0
+ `define RX_EN_1
+ `define RX_CAP_NCHAN 3'd2
+ `ifdef RX_DIG_ON
+ `define RX_EN_DIG_0
+ `define RX_EN_DIG_1
+ `define RX_CAP_DIG 1
+ `endif
+ `endif
+
+ `ifdef RX_QUAD
+ `define RX_EN_0
+ `define RX_EN_1
+ `define RX_EN_2
+ `define RX_EN_3
+ `define RX_CAP_NCHAN 3'd4
+ `ifdef RX_DIG_ON
+ `define RX_EN_DIG_0
+ `define RX_EN_DIG_1
+ `define RX_CAP_DIG 1
+ `endif
+ `endif
+
+ `ifdef RX_HB_ON
+ `define RX_CAP_HB 1
+ `else
+ `define RX_CAP_HB 0
+ `endif
+
+`else // !ifdef RX_ON
+
+ `define RX_CAP_NCHAN 3'd0
+ `define RX_CAP_HB 0
+
+`endif // !ifdef RX_ON
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib (from rev 7618,
gnuradio/trunk/gr-gpio/src/fpga/lib)
Property changes on: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/Makefile.am
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/Makefile.am (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/lib/Makefile.am)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/Makefile.am
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/Makefile.am
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,28 @@
+#
+# Copyright 2007 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+SUBDIRS =
+
+EXTRA_DIST = \
+ gpio_input.v \
+ io_pins.v \
+ rx_chain_dig.v \
+ tx_chain_dig.v
\ No newline at end of file
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/gpio_input.v
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/gpio_input.v (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/lib/gpio_input.v)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/gpio_input.v
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/gpio_input.v
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,80 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2008 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+`include "../../../../usrp/firmware/include/fpga_regs_common.v"
+`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
+
+module gpio_input
+ (input clock, input reset, input enable,
+ input out_strobe,
+ input wire [6:0] serial_addr, input wire [31:0] serial_data, input
serial_strobe,
+ input wire [15:0] io_rx_a_in, input wire [15:0] io_rx_b_in,
+ //input wire [15:0] io_tx_a_in, input wire [15:0] io_tx_b_in,
+ output reg rx_dig0_i, output reg rx_dig0_q,
+ output reg rx_dig1_i, output reg rx_dig1_q );
+
+ // Buffer at input to chip
+
+ reg rx_dig_rx_a_a,rx_dig_rx_b_a,rx_dig_rx_a_b,rx_dig_rx_b_b;
+ //TODO possibly use a flancter here
+ //This code can optionally be extended to do streaming input from gpio of
tx boards
+ //The code can also be extended to input more bits
+
+ always @(posedge clock)
+ begin
+ //This is the first point where is determined which physical input
gpio pins are used for streaming digital input
+ //The other point is the code which overrides these pins as input (oe
= 0)
+ //rx_dig_tx_a_a <= #1 io_tx_a_in[14];
+ //rx_dig_tx_b_a <= #1 io_tx_a_in[15];
+ rx_dig_rx_a_a <= #1 io_rx_a_in[14];
+ rx_dig_rx_b_a <= #1 io_rx_a_in[15];
+ //rx_dig_tx_a_b <= #1 io_tx_b_in[14];
+ //rx_dig_tx_b_b <= #1 io_tx_b_in[15];
+ rx_dig_rx_a_b <= #1 io_rx_b_in[14];
+ rx_dig_rx_b_b <= #1 io_rx_b_in[15];
+ end
+
+ // Now mux to the appropriate outputs
+ wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux;
+ wire rx_realsignals;
+ wire [3:0] rx_numchan;//not used here
+ //TODO This setting reg readout is a duplicate of the one in
adc_interface.v.
+ // Change code so this is done in only one place, or give this code its
own register.
+ setting_reg #(`FR_RX_MUX)
sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),
+
.in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]}));
+ //assign rx_numchan[0] = 1'b0;
+
+ always @(posedge clock)
+ if (out_strobe) //out_strobe determines the time at which the digital
inputs are sampled (with a delay of one sample)
+ begin
+ rx_dig0_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? rx_dig_rx_b_b :
rx_dig_rx_a_b) : (ddc0mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
+ rx_dig0_q <= #1 rx_realsignals ? 1'b0 : ddc0mux[3] ? (ddc0mux[2] ?
rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
+ rx_dig1_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? rx_dig_rx_b_b :
rx_dig_rx_a_b) : (ddc1mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
+ rx_dig1_q <= #1 rx_realsignals ? 1'b0 : ddc1mux[3] ? (ddc1mux[2] ?
rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
+ //rx_dig2_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? rx_dig_rx_b_b :
rx_dig_rx_a_b) : (ddc2mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
+ //rx_dig2_q <= #1 rx_realsignals ? 1'b0 : ddc2mux[3] ? (ddc2mux[2] ?
rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
+ //rx_dig3_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? rx_dig_rx_b_b :
rx_dig_rx_a_b) : (ddc3mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
+ //rx_dig3_q <= #1 rx_realsignals ? 1'b0 : ddc3mux[3] ? (ddc3mux[2] ?
rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
+ end
+
+endmodule // gpio_input
+
+
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/io_pins.v
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/io_pins.v (from rev
7618, gnuradio/trunk/gr-gpio/src/fpga/lib/io_pins.v)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/io_pins.v
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/io_pins.v
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,55 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2005,2006 Matt Ettus
+// Copyright (C) 2008 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+`include "../../../../usrp/firmware/include/fpga_regs_common.v"
+`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
+
+module io_pins
+ ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2,
inout wire [15:0] io_3,
+ input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2,
input wire [15:0] reg_3,
+ input wire [15:0] io_0_force_output, input wire [15:0] io_2_force_output,
+ input wire [15:0] io_1_force_input, input wire [15:0] io_3_force_input,
+ input clock, input rx_reset, input tx_reset,
+ input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
+
+ reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe;
+
+ bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe |
io_0_force_output),.reg_val(reg_0));
+ bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe &
(~io_1_force_input)),.reg_val(reg_1));
+ bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe |
io_2_force_output),.reg_val(reg_2));
+ bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe &
(~io_3_force_input)),.reg_val(reg_3));
+
+ // Upper 16 bits are mask for lower 16
+ always @(posedge clock)
+ if(serial_strobe)
+ case(serial_addr)
+ `FR_OE_0 : io_0_oe
+ <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] &
serial_data[31:16] );
+ `FR_OE_1 : io_1_oe
+ <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] &
serial_data[31:16] );
+ `FR_OE_2 : io_2_oe
+ <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] &
serial_data[31:16] );
+ `FR_OE_3 : io_3_oe
+ <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] &
serial_data[31:16] );
+ endcase // case(serial_addr)
+
+endmodule // io_pins
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/rx_chain_dig.v
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/rx_chain_dig.v
(from rev 7618, gnuradio/trunk/gr-gpio/src/fpga/lib/rx_chain_dig.v)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/rx_chain_dig.v
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/rx_chain_dig.v
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,43 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2008 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+// Following defines conditionally include RX path circuitry
+
+`include "../top/config.vh" // resolved relative to project root
+
+module rx_chain_dig
+ (input clock,
+ input reset,
+ input enable,
+ input wire [15:0] i_in_ana,
+ input wire [15:0] q_in_ana,
+ input wire i_in_dig,
+ input wire q_in_dig,
+ output wire [15:0] i_out,
+ output wire [15:0] q_out
+ );
+
+ //assign upper 15 bits of output to analog input,
+ // discards lsb of analog input and replace with digital input bit (which
comes from gpio)
+ assign i_out = (enable)?{i_in_ana[15:1],i_in_dig}:i_in_ana;
+ assign q_out = (enable)?{q_in_ana[15:1],q_in_dig}:q_in_ana;
+
+endmodule // rx_chain_dig
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/tx_chain_dig.v
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/tx_chain_dig.v
(from rev 7618, gnuradio/trunk/gr-gpio/src/fpga/lib/tx_chain_dig.v)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/tx_chain_dig.v
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/lib/tx_chain_dig.v
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,42 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2008 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+module tx_chain_dig
+ (input clock,
+ input reset,
+ input enable,
+ input wire [15:0] i_in,
+ input wire [15:0] q_in,
+ output wire [15:0] i_out_ana,
+ output wire [15:0] q_out_ana,
+ output wire i_out_dig,
+ output wire q_out_dig
+ );
+
+ //assign upper 15 bits to analog processing, discard lowest bit
+ //output lower two bits of I and Q as digital signal (to be output on gpio
pins)
+ assign i_out_ana = (enable)?{i_in[15:1],1'b0}:i_in;
+ assign q_out_ana = (enable)?{q_in[15:1],1'b0}:q_in;
+ //wire out_dig = (enable)?{i_in[0],q_in[0]}:2'b00;
+ assign i_out_dig = (enable)?i_in[0]:1'b0;
+ assign q_out_dig = (enable)?q_in[0]:1'b0;
+
+endmodule // tx_chain_dig
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top (from rev 7618,
gnuradio/trunk/gr-gpio/src/fpga/top)
Property changes on: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
db
prev*.*
*.summary
*.qws
*.rpt
*.done
*.pin
*.sof
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/Makefile.am
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/Makefile.am (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/top/Makefile.am)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/Makefile.am
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/Makefile.am
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,55 @@
+#
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+include $(top_srcdir)/Makefile.common
+
+datadir = $(prefix)/share/usrp
+
+datarev2dir = $(datadir)/rev2
+
+datarev4dir = $(datadir)/rev4
+
+datarev2_DATA = usrp_gpio.rbf
+
+datarev4_DATA = usrp_gpio.rbf
+
+RBFS = usrp_gpio.rbf
+
+EXTRA_DIST = \
+ config.vh \
+ usrp_gpio.csf \
+ usrp_gpio.esf \
+ usrp_gpio.psf \
+ usrp_gpio.qpf \
+ usrp_gpio.qsf \
+ usrp_gpio.v \
+ $(RBFS)
+
+MOSTLYCLEANFILES = \
+ db/* \
+ *.rpt \
+ *.summary \
+ *.qws \
+ *.smsg \
+ *.done \
+ *.pin \
+ *.sof \
+ *~
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/config.vh
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/config.vh (from rev
7618, gnuradio/trunk/gr-gpio/src/fpga/top/config.vh)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/config.vh
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/config.vh
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,57 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006,2007 Matt Ettus
+// Copyright (C) 2008 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+// ====================================================================
+// User control over what parts get included
+//
+// >>>> EDIT ONLY THIS SECTION <<<<
+// Uncomment only ONE configuration
+// ====================================================================
+
+// ====================================================================
+// FIXME drive configuration selection from the command line and/or gui
+// ====================================================================
+
+// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
+//`include "../include/common_config_1rxhb_1tx.vh"
+
+// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
+// `include "../include/common_config_2rxhb_2tx.vh"
+
+// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels with
digital output (lsb of I and Q) on gpio pins
+ `include "../include/common_config_2rxhb_2txdig.vh"
+
+// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
+//`include "../include/common_config_4rx_0tx.vh"
+
+// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit
channels
+//`include "../include/common_config_2rxhb_0tx.vh"
+
+// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit
channels
+//`include "../include/common_config_2rx_0tx.vh"
+
+// Add other "known to fit" configurations here...
+
+// ====================================================================
+// Now include the common footer
+// ====================================================================
+ `include "../include/common_config_bottom.vh"
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.csf
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.csf (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/top/usrp_gpio.csf)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.csf
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.csf
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,444 @@
+COMPILER_SETTINGS
+{
+ IO_PLACEMENT_OPTIMIZATION = OFF;
+ ENABLE_DRC_SETTINGS = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
+ PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ TRUE_WYSIWYG_FLOW = OFF;
+ SEED = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN
1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO
4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = "NORMAL COMPILATION";
+ OPTIMIZE_HOLD_TIMING = OFF;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = OFF;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |usrp_gpio;
+ ROUTING_BACK_ANNOTATION_MODE = OFF;
+ INC_PLC_MODE = OFF;
+ FIT_ONLY_ONE_ATTEMPT = OFF;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = SLD_HUB_INST;
+ HUB_ENTITY_NAME = SLD_HUB;
+}
+SIGNALTAP_LOGIC_ANALYZER_SETTINGS
+{
+ ENABLE_SIGNALTAP = Off;
+ AUTO_ENABLE_SMART_COMPILE = On;
+}
+CHIP(usrp_gpio)
+{
+ DEVICE = EP1C12Q240C8;
+ DEVICE_FILTER_PACKAGE = "ANY QFP";
+ DEVICE_FILTER_PIN_COUNT = 240;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ USER_START_UP_CLOCK = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ USE_CONFIGURATION_DEVICE = OFF;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ STRATIX_UPDATE_MODE = STANDARD;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ COMPRESSION_MODE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ GENERATE_RBF_FILE = ON;
+ GENERATE_HEX_FILE = OFF;
+ SECURITY_BIT = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ GENERATE_SVF_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+ BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED";
+ STRATIX_DEVICE_IO_STANDARD = LVTTL;
+ CLOCK_SOURCE = INTERNAL;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ SCLK : LOCATION = Pin_101;
+ SDI : LOCATION = Pin_100;
+ SEN : LOCATION = Pin_98;
+ SLD : LOCATION = Pin_95;
+ adc1_data[0] : LOCATION = Pin_5;
+ adc1_data[10] : LOCATION = Pin_235;
+ adc1_data[11] : LOCATION = Pin_234;
+ adc1_data[1] : LOCATION = Pin_4;
+ adc1_data[2] : LOCATION = Pin_3;
+ adc1_data[3] : LOCATION = Pin_2;
+ adc1_data[4] : LOCATION = Pin_1;
+ adc1_data[4] : IO_STANDARD = LVTTL;
+ adc1_data[5] : LOCATION = Pin_240;
+ adc1_data[6] : LOCATION = Pin_239;
+ adc1_data[7] : LOCATION = Pin_238;
+ adc1_data[8] : LOCATION = Pin_237;
+ adc1_data[9] : LOCATION = Pin_236;
+ adc2_data[0] : LOCATION = Pin_20;
+ adc2_data[10] : LOCATION = Pin_8;
+ adc2_data[11] : LOCATION = Pin_7;
+ adc2_data[1] : LOCATION = Pin_19;
+ adc2_data[2] : LOCATION = Pin_18;
+ adc2_data[3] : LOCATION = Pin_17;
+ adc2_data[4] : LOCATION = Pin_16;
+ adc2_data[5] : LOCATION = Pin_15;
+ adc2_data[6] : LOCATION = Pin_14;
+ adc2_data[7] : LOCATION = Pin_13;
+ adc2_data[8] : LOCATION = Pin_12;
+ adc2_data[9] : LOCATION = Pin_11;
+ adc3_data[0] : LOCATION = Pin_200;
+ adc3_data[10] : LOCATION = Pin_184;
+ adc3_data[11] : LOCATION = Pin_183;
+ adc3_data[1] : LOCATION = Pin_197;
+ adc3_data[2] : LOCATION = Pin_196;
+ adc3_data[3] : LOCATION = Pin_195;
+ adc3_data[4] : LOCATION = Pin_194;
+ adc3_data[5] : LOCATION = Pin_193;
+ adc3_data[6] : LOCATION = Pin_188;
+ adc3_data[7] : LOCATION = Pin_187;
+ adc3_data[8] : LOCATION = Pin_186;
+ adc3_data[9] : LOCATION = Pin_185;
+ adc4_data[0] : LOCATION = Pin_222;
+ adc4_data[10] : LOCATION = Pin_203;
+ adc4_data[11] : LOCATION = Pin_202;
+ adc4_data[1] : LOCATION = Pin_219;
+ adc4_data[2] : LOCATION = Pin_217;
+ adc4_data[3] : LOCATION = Pin_216;
+ adc4_data[4] : LOCATION = Pin_215;
+ adc4_data[5] : LOCATION = Pin_214;
+ adc4_data[6] : LOCATION = Pin_213;
+ adc4_data[7] : LOCATION = Pin_208;
+ adc4_data[8] : LOCATION = Pin_207;
+ adc4_data[9] : LOCATION = Pin_206;
+ adc_oeb[0] : LOCATION = Pin_228;
+ adc_oeb[1] : LOCATION = Pin_21;
+ adc_oeb[2] : LOCATION = Pin_181;
+ adc_oeb[3] : LOCATION = Pin_218;
+ adc_otr[0] : LOCATION = Pin_233;
+ adc_otr[1] : LOCATION = Pin_6;
+ adc_otr[2] : LOCATION = Pin_182;
+ adc_otr[3] : LOCATION = Pin_201;
+ adclk0 : LOCATION = Pin_224;
+ adclk1 : LOCATION = Pin_226;
+ clk0 : LOCATION = Pin_28;
+ clk0 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk0 : IO_STANDARD = LVTTL;
+ clk1 : LOCATION = Pin_29;
+ clk1 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk1 : IO_STANDARD = LVTTL;
+ clk3 : LOCATION = Pin_152;
+ clk3 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk3 : IO_STANDARD = LVTTL;
+ clk_120mhz : LOCATION = Pin_153;
+ clk_120mhz : IO_STANDARD = LVTTL;
+ clk_out : LOCATION = Pin_63;
+ clk_out : IO_STANDARD = LVTTL;
+ dac1_data[0] : LOCATION = Pin_165;
+ dac1_data[10] : LOCATION = Pin_177;
+ dac1_data[11] : LOCATION = Pin_178;
+ dac1_data[12] : LOCATION = Pin_179;
+ dac1_data[13] : LOCATION = Pin_180;
+ dac1_data[1] : LOCATION = Pin_166;
+ dac1_data[2] : LOCATION = Pin_167;
+ dac1_data[3] : LOCATION = Pin_168;
+ dac1_data[4] : LOCATION = Pin_169;
+ dac1_data[5] : LOCATION = Pin_170;
+ dac1_data[6] : LOCATION = Pin_173;
+ dac1_data[7] : LOCATION = Pin_174;
+ dac1_data[8] : LOCATION = Pin_175;
+ dac1_data[9] : LOCATION = Pin_176;
+ dac2_data[0] : LOCATION = Pin_159;
+ dac2_data[10] : LOCATION = Pin_163;
+ dac2_data[11] : LOCATION = Pin_139;
+ dac2_data[12] : LOCATION = Pin_164;
+ dac2_data[13] : LOCATION = Pin_138;
+ dac2_data[1] : LOCATION = Pin_158;
+ dac2_data[2] : LOCATION = Pin_160;
+ dac2_data[3] : LOCATION = Pin_156;
+ dac2_data[4] : LOCATION = Pin_161;
+ dac2_data[5] : LOCATION = Pin_144;
+ dac2_data[6] : LOCATION = Pin_162;
+ dac2_data[7] : LOCATION = Pin_141;
+ dac2_data[8] : LOCATION = Pin_143;
+ dac2_data[9] : LOCATION = Pin_140;
+ dac3_data[0] : LOCATION = Pin_122;
+ dac3_data[10] : LOCATION = Pin_134;
+ dac3_data[11] : LOCATION = Pin_135;
+ dac3_data[12] : LOCATION = Pin_136;
+ dac3_data[13] : LOCATION = Pin_137;
+ dac3_data[1] : LOCATION = Pin_123;
+ dac3_data[2] : LOCATION = Pin_124;
+ dac3_data[3] : LOCATION = Pin_125;
+ dac3_data[4] : LOCATION = Pin_126;
+ dac3_data[5] : LOCATION = Pin_127;
+ dac3_data[6] : LOCATION = Pin_128;
+ dac3_data[7] : LOCATION = Pin_131;
+ dac3_data[8] : LOCATION = Pin_132;
+ dac3_data[9] : LOCATION = Pin_133;
+ dac4_data[0] : LOCATION = Pin_104;
+ dac4_data[10] : LOCATION = Pin_118;
+ dac4_data[11] : LOCATION = Pin_119;
+ dac4_data[12] : LOCATION = Pin_120;
+ dac4_data[13] : LOCATION = Pin_121;
+ dac4_data[1] : LOCATION = Pin_105;
+ dac4_data[2] : LOCATION = Pin_106;
+ dac4_data[3] : LOCATION = Pin_107;
+ dac4_data[4] : LOCATION = Pin_108;
+ dac4_data[5] : LOCATION = Pin_113;
+ dac4_data[6] : LOCATION = Pin_114;
+ dac4_data[7] : LOCATION = Pin_115;
+ dac4_data[8] : LOCATION = Pin_116;
+ dac4_data[9] : LOCATION = Pin_117;
+ enable_rx : LOCATION = Pin_88;
+ enable_tx : LOCATION = Pin_93;
+ gndbus[0] : LOCATION = Pin_223;
+ gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[0] : IO_STANDARD = LVTTL;
+ gndbus[1] : LOCATION = Pin_225;
+ gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[1] : IO_STANDARD = LVTTL;
+ gndbus[2] : LOCATION = Pin_227;
+ gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[2] : IO_STANDARD = LVTTL;
+ gndbus[3] : LOCATION = Pin_62;
+ gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[3] : IO_STANDARD = LVTTL;
+ gndbus[4] : LOCATION = Pin_64;
+ gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[4] : IO_STANDARD = LVTTL;
+ misc_pins[0] : LOCATION = Pin_87;
+ misc_pins[0] : IO_STANDARD = LVTTL;
+ misc_pins[10] : LOCATION = Pin_76;
+ misc_pins[10] : IO_STANDARD = LVTTL;
+ misc_pins[11] : LOCATION = Pin_74;
+ misc_pins[11] : IO_STANDARD = LVTTL;
+ misc_pins[1] : LOCATION = Pin_86;
+ misc_pins[1] : IO_STANDARD = LVTTL;
+ misc_pins[2] : LOCATION = Pin_85;
+ misc_pins[2] : IO_STANDARD = LVTTL;
+ misc_pins[3] : LOCATION = Pin_84;
+ misc_pins[3] : IO_STANDARD = LVTTL;
+ misc_pins[4] : LOCATION = Pin_83;
+ misc_pins[4] : IO_STANDARD = LVTTL;
+ misc_pins[5] : LOCATION = Pin_82;
+ misc_pins[5] : IO_STANDARD = LVTTL;
+ misc_pins[6] : LOCATION = Pin_79;
+ misc_pins[6] : IO_STANDARD = LVTTL;
+ misc_pins[7] : LOCATION = Pin_78;
+ misc_pins[7] : IO_STANDARD = LVTTL;
+ misc_pins[8] : LOCATION = Pin_77;
+ misc_pins[8] : IO_STANDARD = LVTTL;
+ misc_pins[9] : LOCATION = Pin_75;
+ misc_pins[9] : IO_STANDARD = LVTTL;
+ reset : LOCATION = Pin_94;
+ usbclk : LOCATION = Pin_55;
+ usbctl[0] : LOCATION = Pin_56;
+ usbctl[1] : LOCATION = Pin_54;
+ usbctl[2] : LOCATION = Pin_53;
+ usbctl[3] : LOCATION = Pin_58;
+ usbctl[4] : LOCATION = Pin_57;
+ usbctl[5] : LOCATION = Pin_44;
+ usbdata[0] : LOCATION = Pin_73;
+ usbdata[10] : LOCATION = Pin_41;
+ usbdata[11] : LOCATION = Pin_39;
+ usbdata[12] : LOCATION = Pin_38;
+ usbdata[12] : IO_STANDARD = LVTTL;
+ usbdata[13] : LOCATION = Pin_37;
+ usbdata[14] : LOCATION = Pin_24;
+ usbdata[15] : LOCATION = Pin_23;
+ usbdata[1] : LOCATION = Pin_68;
+ usbdata[2] : LOCATION = Pin_67;
+ usbdata[3] : LOCATION = Pin_66;
+ usbdata[4] : LOCATION = Pin_65;
+ usbdata[5] : LOCATION = Pin_61;
+ usbdata[6] : LOCATION = Pin_60;
+ usbdata[7] : LOCATION = Pin_59;
+ usbdata[8] : LOCATION = Pin_43;
+ usbdata[9] : LOCATION = Pin_42;
+ usbrdy[0] : LOCATION = Pin_45;
+ usbrdy[1] : LOCATION = Pin_46;
+ usbrdy[2] : LOCATION = Pin_47;
+ usbrdy[3] : LOCATION = Pin_48;
+ usbrdy[4] : LOCATION = Pin_49;
+ usbrdy[5] : LOCATION = Pin_50;
+ clear_status : LOCATION = Pin_99;
+}
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.esf
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.esf (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/top/usrp_gpio.esf)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.esf
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.esf
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,14 @@
+SIMULATOR_SETTINGS
+{
+ ESTIMATE_POWER_CONSUMPTION = OFF;
+ GLITCH_INTERVAL = 1NS;
+ GLITCH_DETECTION = OFF;
+ SIMULATION_COVERAGE = ON;
+ CHECK_OUTPUTS = OFF;
+ SETUP_HOLD_DETECTION = OFF;
+ POWER_ESTIMATION_START_TIME = "0 NS";
+ ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
+ SIMULATION_MODE = TIMING;
+ START_TIME = 0NS;
+ USE_COMPILER_SETTINGS = usrp_gpio;
+}
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.psf
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.psf (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/top/usrp_gpio.psf)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.psf
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.psf
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,312 @@
+DEFAULT_DESIGN_ASSISTANT_SETTINGS
+{
+ HCPY_ALOAD_SIGNALS = OFF;
+ HCPY_VREF_PINS = OFF;
+ HCPY_CAT = OFF;
+ HCPY_ILLEGAL_HC_DEV_PKG = OFF;
+ ACLK_RULE_IMSZER_ADOMAIN = OFF;
+ ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
+ ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
+ ACLK_CAT = OFF;
+ SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
+ SIGNALRACE_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
+ NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_DLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
+ NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
+ NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
+ NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
+ NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
+ NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
+ NONSYNCHSTRUCT_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
+ TIMING_RULE_COIN_CLKEDGE = OFF;
+ TIMING_RULE_SHIFT_REG = OFF;
+ TIMING_RULE_HIGH_FANOUTS = OFF;
+ TIMING_CAT = OFF;
+ RESET_RULE_ALL = OFF;
+ RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_REG_ASNYCH = OFF;
+ RESET_RULE_COMB_ASYNCH_RESET = OFF;
+ RESET_RULE_IMSYNCH_EXRESET = OFF;
+ RESET_RULE_UNSYNCH_EXRESET = OFF;
+ RESET_RULE_INPINS_RESETNET = OFF;
+ RESET_CAT = OFF;
+ CLK_RULE_ALL = OFF;
+ CLK_RULE_MIX_EDGES = OFF;
+ CLK_RULE_CLKNET_CLKSPINES = OFF;
+ CLK_RULE_INPINS_CLKNET = OFF;
+ CLK_RULE_GATING_SCHEME = OFF;
+ CLK_RULE_INV_CLOCK = OFF;
+ CLK_RULE_COMB_CLOCK = OFF;
+ CLK_CAT = OFF;
+ HCPY_EXCEED_USER_IO_USAGE = OFF;
+ HCPY_EXCEED_RAM_USAGE = OFF;
+ NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
+ SIGNALRACE_RULE_TRISTATE = OFF;
+ ASSG_RULE_MISSING_TIMING = OFF;
+ ASSG_RULE_MISSING_FMAX = OFF;
+ ASSG_CAT = OFF;
+}
+SYNTHESIS_FITTING_SETTINGS
+{
+ AUTO_SHIFT_REGISTER_RECOGNITION = ON;
+ AUTO_DSP_RECOGNITION = ON;
+ AUTO_RAM_RECOGNITION = ON;
+ REMOVE_DUPLICATE_LOGIC = ON;
+ AUTO_TURBO_BIT = ON;
+ AUTO_MERGE_PLLS = ON;
+ AUTO_OPEN_DRAIN_PINS = ON;
+ AUTO_PARALLEL_EXPANDERS = ON;
+ AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF;
+ AUTO_FAST_OUTPUT_REGISTERS = OFF;
+ AUTO_FAST_INPUT_REGISTERS = OFF;
+ AUTO_CASCADE_CHAINS = ON;
+ AUTO_CARRY_CHAINS = ON;
+ AUTO_DELAY_CHAINS = ON;
+ MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
+ PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
+ CASCADE_CHAIN_LENGTH = 2;
+ STRATIX_CARRY_CHAIN_LENGTH = 70;
+ MERCURY_CARRY_CHAIN_LENGTH = 48;
+ FLEX10K_CARRY_CHAIN_LENGTH = 32;
+ FLEX6K_CARRY_CHAIN_LENGTH = 32;
+ CARRY_CHAIN_LENGTH = 48;
+ CARRY_OUT_PINS_LCELL_INSERT = ON;
+ NORMAL_LCELL_INSERT = ON;
+ AUTO_LCELL_INSERTION = ON;
+ ALLOW_XOR_GATE_USAGE = ON;
+ AUTO_PACKED_REGISTERS_STRATIX = NORMAL;
+ AUTO_PACKED_REGISTERS = OFF;
+ AUTO_PACKED_REG_CYCLONE = NORMAL;
+ FLEX10K_OPTIMIZATION_TECHNIQUE = AREA;
+ FLEX6K_OPTIMIZATION_TECHNIQUE = AREA;
+ MERCURY_OPTIMIZATION_TECHNIQUE = AREA;
+ APEX20K_OPTIMIZATION_TECHNIQUE = SPEED;
+ MAX7000_OPTIMIZATION_TECHNIQUE = SPEED;
+ STRATIX_OPTIMIZATION_TECHNIQUE = SPEED;
+ CYCLONE_OPTIMIZATION_TECHNIQUE = AREA;
+ FLEX10K_TECHNOLOGY_MAPPER = LUT;
+ FLEX6K_TECHNOLOGY_MAPPER = LUT;
+ MERCURY_TECHNOLOGY_MAPPER = LUT;
+ APEX20K_TECHNOLOGY_MAPPER = LUT;
+ MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM";
+ STRATIX_TECHNOLOGY_MAPPER = LUT;
+ AUTO_IMPLEMENT_IN_ROM = OFF;
+ AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
+ AUTO_GLOBAL_REGISTER_CONTROLS = ON;
+ AUTO_GLOBAL_OE = ON;
+ AUTO_GLOBAL_CLOCK = ON;
+ USE_LPM_FOR_AHDL_OPERATORS = ON;
+ LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
+ ENABLE_BUS_HOLD_CIRCUITRY = OFF;
+ WEAK_PULL_UP_RESISTOR = OFF;
+ TURBO_BIT = ON;
+ MAX7000_IGNORE_SOFT_BUFFERS = OFF;
+ IGNORE_SOFT_BUFFERS = ON;
+ MAX7000_IGNORE_LCELL_BUFFERS = AUTO;
+ IGNORE_LCELL_BUFFERS = OFF;
+ IGNORE_ROW_GLOBAL_BUFFERS = OFF;
+ IGNORE_GLOBAL_BUFFERS = OFF;
+ IGNORE_CASCADE_BUFFERS = OFF;
+ IGNORE_CARRY_BUFFERS = OFF;
+ REMOVE_DUPLICATE_REGISTERS = ON;
+ REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
+ ALLOW_POWER_UP_DONT_CARE = ON;
+ PCI_IO = OFF;
+ NOT_GATE_PUSH_BACK = ON;
+ SLOW_SLEW_RATE = OFF;
+ DSP_BLOCK_BALANCING = AUTO;
+ STATE_MACHINE_PROCESSING = AUTO;
+}
+DEFAULT_HARDCOPY_SETTINGS
+{
+ HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
+}
+DEFAULT_TIMING_REQUIREMENTS
+{
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ RUN_ALL_TIMING_ANALYSES = ON;
+ IGNORE_CLOCK_SETTINGS = OFF;
+ DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
+ CUT_OFF_IO_PIN_FEEDBACK = ON;
+ CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+ CUT_OFF_READ_DURING_WRITE_PATHS = ON;
+ CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
+ DO_MIN_ANALYSIS = ON;
+ DO_MIN_TIMING = OFF;
+ NUMBER_OF_PATHS_TO_REPORT = 200;
+ NUMBER_OF_DESTINATION_TO_REPORT = 10;
+ NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
+ MAX_SCC_SIZE = 50;
+}
+HDL_SETTINGS
+{
+ VERILOG_INPUT_VERSION = VERILOG_2001;
+ ENABLE_IP_DEBUG = OFF;
+ VHDL_INPUT_VERSION = VHDL93;
+ VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
+}
+PROJECT_INFO(usrp_gpio)
+{
+ ORIGINAL_QUARTUS_VERSION = 3.0;
+ PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003";
+ LAST_QUARTUS_VERSION = 3.0;
+ SHOW_REGISTRATION_MESSAGE = ON;
+ USER_LIBRARIES = "e:\usrp\fpga\megacells";
+}
+THIRD_PARTY_EDA_TOOLS(usrp_gpio)
+{
+ EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
+ EDA_SIMULATION_TOOL = "<NONE>";
+ EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
+ EDA_BOARD_DESIGN_TOOL = "<NONE>";
+ EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
+ EDA_RESYNTHESIS_TOOL = "<NONE>";
+}
+EDA_TOOL_SETTINGS(eda_design_synthesis)
+{
+ EDA_INPUT_GND_NAME = GND;
+ EDA_INPUT_VCC_NAME = VCC;
+ EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_INPUT_DATA_FORMAT = EDIF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_simulation)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_timing_analysis)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ EDA_LAUNCH_CMD_LINE_TOOL = OFF;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_board_design)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_formal_verification)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_palace)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ RESYNTHESIS_RETIMING = FULL;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+}
+CLOCK(clk_120mhz)
+{
+ FMAX_REQUIREMENT = "120.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(usbclk)
+{
+ FMAX_REQUIREMENT = "48.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(SCLK)
+{
+ FMAX_REQUIREMENT = "1.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk0)
+{
+ FMAX_REQUIREMENT = "60.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk1)
+{
+ FMAX_REQUIREMENT = "60.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qpf
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qpf (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/top/usrp_gpio.qpf)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qpf
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qpf
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.0"
+DATE = "17:10:11 December 20, 2004"
+
+
+# Active Revisions
+
+PROJECT_REVISION = "usrp_gpio"
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qsf
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qsf (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/top/usrp_gpio.qsf)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qsf
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.qsf
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,410 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# usrp_gpio_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
+set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
+
+# Pin & Location Assignments
+# ==========================
+set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
+set_location_assignment PIN_29 -to SCLK
+set_location_assignment PIN_117 -to SDI
+set_location_assignment PIN_28 -to usbclk
+set_location_assignment PIN_107 -to usbctl[0]
+set_location_assignment PIN_106 -to usbctl[1]
+set_location_assignment PIN_105 -to usbctl[2]
+set_location_assignment PIN_100 -to usbdata[0]
+set_location_assignment PIN_84 -to usbdata[10]
+set_location_assignment PIN_83 -to usbdata[11]
+set_location_assignment PIN_82 -to usbdata[12]
+set_location_assignment PIN_79 -to usbdata[13]
+set_location_assignment PIN_78 -to usbdata[14]
+set_location_assignment PIN_77 -to usbdata[15]
+set_location_assignment PIN_99 -to usbdata[1]
+set_location_assignment PIN_98 -to usbdata[2]
+set_location_assignment PIN_95 -to usbdata[3]
+set_location_assignment PIN_94 -to usbdata[4]
+set_location_assignment PIN_93 -to usbdata[5]
+set_location_assignment PIN_88 -to usbdata[6]
+set_location_assignment PIN_87 -to usbdata[7]
+set_location_assignment PIN_86 -to usbdata[8]
+set_location_assignment PIN_85 -to usbdata[9]
+set_location_assignment PIN_104 -to usbrdy[0]
+set_location_assignment PIN_101 -to usbrdy[1]
+set_location_assignment PIN_76 -to FX2_1
+set_location_assignment PIN_75 -to FX2_2
+set_location_assignment PIN_74 -to FX2_3
+set_location_assignment PIN_116 -to io_rx_a[0]
+set_location_assignment PIN_115 -to io_rx_a[1]
+set_location_assignment PIN_114 -to io_rx_a[2]
+set_location_assignment PIN_113 -to io_rx_a[3]
+set_location_assignment PIN_108 -to io_rx_a[4]
+set_location_assignment PIN_195 -to io_rx_a[5]
+set_location_assignment PIN_196 -to io_rx_a[6]
+set_location_assignment PIN_197 -to io_rx_a[7]
+set_location_assignment PIN_200 -to io_rx_a[8]
+set_location_assignment PIN_201 -to io_rx_a[9]
+set_location_assignment PIN_202 -to io_rx_a[10]
+set_location_assignment PIN_203 -to io_rx_a[11]
+set_location_assignment PIN_206 -to io_rx_a[12]
+set_location_assignment PIN_207 -to io_rx_a[13]
+set_location_assignment PIN_208 -to io_rx_a[14]
+set_location_assignment PIN_214 -to io_rx_b[0]
+set_location_assignment PIN_215 -to io_rx_b[1]
+set_location_assignment PIN_216 -to io_rx_b[2]
+set_location_assignment PIN_217 -to io_rx_b[3]
+set_location_assignment PIN_218 -to io_rx_b[4]
+set_location_assignment PIN_219 -to io_rx_b[5]
+set_location_assignment PIN_222 -to io_rx_b[6]
+set_location_assignment PIN_223 -to io_rx_b[7]
+set_location_assignment PIN_224 -to io_rx_b[8]
+set_location_assignment PIN_225 -to io_rx_b[9]
+set_location_assignment PIN_226 -to io_rx_b[10]
+set_location_assignment PIN_227 -to io_rx_b[11]
+set_location_assignment PIN_228 -to io_rx_b[12]
+set_location_assignment PIN_233 -to io_rx_b[13]
+set_location_assignment PIN_234 -to io_rx_b[14]
+set_location_assignment PIN_175 -to io_tx_a[0]
+set_location_assignment PIN_176 -to io_tx_a[1]
+set_location_assignment PIN_177 -to io_tx_a[2]
+set_location_assignment PIN_178 -to io_tx_a[3]
+set_location_assignment PIN_179 -to io_tx_a[4]
+set_location_assignment PIN_180 -to io_tx_a[5]
+set_location_assignment PIN_181 -to io_tx_a[6]
+set_location_assignment PIN_182 -to io_tx_a[7]
+set_location_assignment PIN_183 -to io_tx_a[8]
+set_location_assignment PIN_184 -to io_tx_a[9]
+set_location_assignment PIN_185 -to io_tx_a[10]
+set_location_assignment PIN_186 -to io_tx_a[11]
+set_location_assignment PIN_187 -to io_tx_a[12]
+set_location_assignment PIN_188 -to io_tx_a[13]
+set_location_assignment PIN_193 -to io_tx_a[14]
+set_location_assignment PIN_73 -to io_tx_b[0]
+set_location_assignment PIN_68 -to io_tx_b[1]
+set_location_assignment PIN_67 -to io_tx_b[2]
+set_location_assignment PIN_66 -to io_tx_b[3]
+set_location_assignment PIN_65 -to io_tx_b[4]
+set_location_assignment PIN_64 -to io_tx_b[5]
+set_location_assignment PIN_63 -to io_tx_b[6]
+set_location_assignment PIN_62 -to io_tx_b[7]
+set_location_assignment PIN_61 -to io_tx_b[8]
+set_location_assignment PIN_60 -to io_tx_b[9]
+set_location_assignment PIN_59 -to io_tx_b[10]
+set_location_assignment PIN_58 -to io_tx_b[11]
+set_location_assignment PIN_57 -to io_tx_b[12]
+set_location_assignment PIN_56 -to io_tx_b[13]
+set_location_assignment PIN_55 -to io_tx_b[14]
+set_location_assignment PIN_152 -to master_clk
+set_location_assignment PIN_144 -to rx_a_a[0]
+set_location_assignment PIN_143 -to rx_a_a[1]
+set_location_assignment PIN_141 -to rx_a_a[2]
+set_location_assignment PIN_140 -to rx_a_a[3]
+set_location_assignment PIN_139 -to rx_a_a[4]
+set_location_assignment PIN_138 -to rx_a_a[5]
+set_location_assignment PIN_137 -to rx_a_a[6]
+set_location_assignment PIN_136 -to rx_a_a[7]
+set_location_assignment PIN_135 -to rx_a_a[8]
+set_location_assignment PIN_134 -to rx_a_a[9]
+set_location_assignment PIN_133 -to rx_a_a[10]
+set_location_assignment PIN_132 -to rx_a_a[11]
+set_location_assignment PIN_23 -to rx_a_b[0]
+set_location_assignment PIN_21 -to rx_a_b[1]
+set_location_assignment PIN_20 -to rx_a_b[2]
+set_location_assignment PIN_19 -to rx_a_b[3]
+set_location_assignment PIN_18 -to rx_a_b[4]
+set_location_assignment PIN_17 -to rx_a_b[5]
+set_location_assignment PIN_16 -to rx_a_b[6]
+set_location_assignment PIN_15 -to rx_a_b[7]
+set_location_assignment PIN_14 -to rx_a_b[8]
+set_location_assignment PIN_13 -to rx_a_b[9]
+set_location_assignment PIN_12 -to rx_a_b[10]
+set_location_assignment PIN_11 -to rx_a_b[11]
+set_location_assignment PIN_131 -to rx_b_a[0]
+set_location_assignment PIN_128 -to rx_b_a[1]
+set_location_assignment PIN_127 -to rx_b_a[2]
+set_location_assignment PIN_126 -to rx_b_a[3]
+set_location_assignment PIN_125 -to rx_b_a[4]
+set_location_assignment PIN_124 -to rx_b_a[5]
+set_location_assignment PIN_123 -to rx_b_a[6]
+set_location_assignment PIN_122 -to rx_b_a[7]
+set_location_assignment PIN_121 -to rx_b_a[8]
+set_location_assignment PIN_120 -to rx_b_a[9]
+set_location_assignment PIN_119 -to rx_b_a[10]
+set_location_assignment PIN_118 -to rx_b_a[11]
+set_location_assignment PIN_8 -to rx_b_b[0]
+set_location_assignment PIN_7 -to rx_b_b[1]
+set_location_assignment PIN_6 -to rx_b_b[2]
+set_location_assignment PIN_5 -to rx_b_b[3]
+set_location_assignment PIN_4 -to rx_b_b[4]
+set_location_assignment PIN_3 -to rx_b_b[5]
+set_location_assignment PIN_2 -to rx_b_b[6]
+set_location_assignment PIN_240 -to rx_b_b[7]
+set_location_assignment PIN_239 -to rx_b_b[8]
+set_location_assignment PIN_238 -to rx_b_b[9]
+set_location_assignment PIN_237 -to rx_b_b[10]
+set_location_assignment PIN_236 -to rx_b_b[11]
+set_location_assignment PIN_156 -to SDO
+set_location_assignment PIN_153 -to SEN_FPGA
+set_location_assignment PIN_159 -to tx_a[0]
+set_location_assignment PIN_160 -to tx_a[1]
+set_location_assignment PIN_161 -to tx_a[2]
+set_location_assignment PIN_162 -to tx_a[3]
+set_location_assignment PIN_163 -to tx_a[4]
+set_location_assignment PIN_164 -to tx_a[5]
+set_location_assignment PIN_165 -to tx_a[6]
+set_location_assignment PIN_166 -to tx_a[7]
+set_location_assignment PIN_167 -to tx_a[8]
+set_location_assignment PIN_168 -to tx_a[9]
+set_location_assignment PIN_169 -to tx_a[10]
+set_location_assignment PIN_170 -to tx_a[11]
+set_location_assignment PIN_173 -to tx_a[12]
+set_location_assignment PIN_174 -to tx_a[13]
+set_location_assignment PIN_38 -to tx_b[0]
+set_location_assignment PIN_39 -to tx_b[1]
+set_location_assignment PIN_41 -to tx_b[2]
+set_location_assignment PIN_42 -to tx_b[3]
+set_location_assignment PIN_43 -to tx_b[4]
+set_location_assignment PIN_44 -to tx_b[5]
+set_location_assignment PIN_45 -to tx_b[6]
+set_location_assignment PIN_46 -to tx_b[7]
+set_location_assignment PIN_47 -to tx_b[8]
+set_location_assignment PIN_48 -to tx_b[9]
+set_location_assignment PIN_49 -to tx_b[10]
+set_location_assignment PIN_50 -to tx_b[11]
+set_location_assignment PIN_53 -to tx_b[12]
+set_location_assignment PIN_54 -to tx_b[13]
+set_location_assignment PIN_158 -to TXSYNC_A
+set_location_assignment PIN_37 -to TXSYNC_B
+set_location_assignment PIN_235 -to io_rx_b[15]
+set_location_assignment PIN_24 -to io_tx_b[15]
+set_location_assignment PIN_213 -to io_rx_a[15]
+set_location_assignment PIN_194 -to io_tx_a[15]
+set_location_assignment PIN_1 -to MYSTERY_SIGNAL
+
+# Timing Assignments
+# ==================
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name TOP_LEVEL_ENTITY usrp_gpio
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP1C12Q240C8
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name INC_PLC_MODE OFF
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+
+# Timing Analysis Assignments
+# ===========================
+set_global_assignment -name MAX_SCC_SIZE 50
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT
TRI-STATED"
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+
+# Simulator Assignments
+# =====================
+set_global_assignment -name START_TIME "0 ns"
+set_global_assignment -name GLITCH_INTERVAL "1 ns"
+
+# Design Assistant Assignments
+# ============================
+set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
+set_global_assignment -name ASSG_CAT OFF
+set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
+set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
+set_global_assignment -name CLK_CAT OFF
+set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
+set_global_assignment -name CLK_RULE_INV_CLOCK OFF
+set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
+set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
+set_global_assignment -name CLK_RULE_MIX_EDGES OFF
+set_global_assignment -name RESET_CAT OFF
+set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name TIMING_CAT OFF
+set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
+set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
+set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
+set_global_assignment -name SIGNALRACE_CAT OFF
+set_global_assignment -name ACLK_CAT OFF
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
+set_global_assignment -name HCPY_CAT OFF
+set_global_assignment -name HCPY_VREF_PINS OFF
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
+set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+
+# LogicLock Region Assignments
+# ============================
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+
+# -----------------
+# start CLOCK(SCLK)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id SCLK
+
+# end CLOCK(SCLK)
+# ---------------
+
+# -----------------------
+# start CLOCK(master_clk)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id master_clk
+
+# end CLOCK(master_clk)
+# ---------------------
+
+# -------------------
+# start CLOCK(usbclk)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id usbclk
+
+# end CLOCK(usbclk)
+# -----------------
+
+# ----------------------
+# start ENTITY(usrp_gpio)
+
+ # Timing Assignments
+ # ==================
+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+
+# end ENTITY(usrp_gpio)
+# --------------------
+
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name VERILOG_FILE usrp_gpio.v
+set_global_assignment -name VERILOG_FILE ../lib/gpio_input.v
+set_global_assignment -name VERILOG_FILE ../lib/io_pins.v
+set_global_assignment -name VERILOG_FILE ../lib/rx_chain_dig.v
+set_global_assignment -name VERILOG_FILE ../lib/tx_chain_dig.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cic_dec_shifter.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/ram16.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/megacells/fifo_4k.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/megacells/bustri.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/megacells/fifo_4k_18.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/acc.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/mult.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/ram16_2sum.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/coeff_rom.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/halfband_decim.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/mac.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/tx_chain.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cic_int_shifter.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_chain.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/master_control.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/tx_buffer.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/phase_acc.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cic_interp.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cic_decim.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/strobe_gen.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/sign_extend.v
\ No newline at end of file
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.rbf
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.rbf (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/top/usrp_gpio.rbf)
===================================================================
(Binary files differ)
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.v
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.v (from
rev 7618, gnuradio/trunk/gr-gpio/src/fpga/top/usrp_gpio.v)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.v
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/fpga/top/usrp_gpio.v
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,467 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003,2004 Matt Ettus
+// Copyright (C) 2008 Corgan Enterprises LLC
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+// Top level module for a full setup with DUCs and DDCs
+
+// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
+// for debugging info. NB, This can kill the m'board and/or d'board if you
+// have anything except basic d'boards installed.
+
+// Uncomment the following to include optional circuitry
+
+`include "../top/config.vh"
+`include "../../../../usrp/firmware/include/fpga_regs_common.v"
+`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
+
+module usrp_gpio
+(output MYSTERY_SIGNAL,
+ input master_clk,
+ input SCLK,
+ input SDI,
+ inout SDO,
+ input SEN_FPGA,
+
+ input FX2_1,
+ output FX2_2,
+ output FX2_3,
+
+ input wire [11:0] rx_a_a,
+ input wire [11:0] rx_b_a,
+ input wire [11:0] rx_a_b,
+ input wire [11:0] rx_b_b,
+
+ output wire [13:0] tx_a,
+ output wire [13:0] tx_b,
+
+ output wire TXSYNC_A,
+ output wire TXSYNC_B,
+
+ // USB interface
+ input usbclk,
+ input wire [2:0] usbctl,
+ output wire [1:0] usbrdy,
+ inout [15:0] usbdata, // NB Careful, inout
+
+ // These are the general purpose i/o's that go to the daughterboard slots
+ inout wire [15:0] io_tx_a,
+ inout wire [15:0] io_tx_b,
+ inout wire [15:0] io_rx_a,
+ inout wire [15:0] io_rx_b
+ );
+ wire [15:0] debugdata,debugctrl;
+ assign MYSTERY_SIGNAL = 1'b0;
+
+ wire clk64,clk128;
+
+ wire WR = usbctl[0];
+ wire RD = usbctl[1];
+ wire OE = usbctl[2];
+
+ wire have_space, have_pkt_rdy;
+ assign usbrdy[0] = have_space;
+ assign usbrdy[1] = have_pkt_rdy;
+
+ wire tx_underrun, rx_overrun;
+ wire clear_status = FX2_1;
+ assign FX2_2 = rx_overrun;
+ assign FX2_3 = tx_underrun;
+
+ wire [15:0] usbdata_out;
+
+ wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
+
+ wire tx_realsignals;
+ wire [3:0] rx_numchan;
+ wire [2:0] tx_numchan;
+
+ wire [7:0] interp_rate, decim_rate;
+ wire [31:0] tx_debugbus, rx_debugbus;
+
+ wire enable_tx, enable_rx;
+ wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
+ wire [7:0] settings;
+
+ // Tri-state bus macro
+ bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
+
+ assign clk64 = master_clk;
+
+ wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
+ wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
+ wire [15:0] ch0rx_ext,ch1rx_ext;
+
+ // TX
+ wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;//analog signals
+ wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; //
bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
+
+ wire strobe_interp, tx_sample_strobe;
+ wire tx_empty;
+
+ wire serial_strobe;
+ wire [6:0] serial_addr;
+ wire [31:0] serial_data;
+
+ reg [15:0] debug_counter;
+ reg [15:0] loopback_i_0,loopback_q_0;
+
+ //TX_DIG streaming digital IO signals
+ wire i_out_dig_0,i_out_dig_1,q_out_dig_0,q_out_dig_1;
+ wire rx_dig0_i, rx_dig0_q,rx_dig1_i,rx_dig1_q;
+
+
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Transmit Side
+`ifdef TX_ON
+
+ tx_buffer tx_buffer
+ ( .usbclk(usbclk), .bus_reset(tx_bus_reset),
+ .usbdata(usbdata),.WR(WR), .have_space(have_space),
+ .tx_underrun(tx_underrun), .clear_status(clear_status),
+ .txclk(clk64), .reset(tx_dsp_reset),
+ .channels({tx_numchan,1'b0}),
+ .tx_i_0(ch0tx),.tx_q_0(ch1tx),
+ .tx_i_1(ch2tx),.tx_q_1(ch3tx),
+ .txstrobe(strobe_interp),
+ .tx_empty(tx_empty),
+ .debugbus(tx_debugbus) );
+
+ `ifdef TX_EN_0
+ tx_chain tx_chain_0
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+ .interpolator_strobe(strobe_interp),.freq(),
+ .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0));
+ `else
+ assign i_out_0=16'd0;
+ assign q_out_0=16'd0;
+ `endif
+
+ `ifdef TX_EN_1
+ tx_chain tx_chain_1
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+ .interpolator_strobe(strobe_interp),.freq(),
+ .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
+ `else
+ assign i_out_1=16'd0;
+ assign q_out_1=16'd0;
+ `endif
+
+
+
+ setting_reg #(`FR_TX_MUX)
+
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
+
+ wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 :
i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 :
i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 :
i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 :
i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+
+ wire tx_dig_a_a = (dac0mux[1] ? (dac0mux[0] ? q_out_dig_1 : i_out_dig_1) :
(dac0mux[0] ? q_out_dig_0 : i_out_dig_0));
+ wire tx_dig_b_a = (dac1mux[1] ? (dac1mux[0] ? q_out_dig_1 : i_out_dig_1) :
(dac1mux[0] ? q_out_dig_0 : i_out_dig_0));
+ wire tx_dig_a_b = (dac2mux[1] ? (dac2mux[0] ? q_out_dig_1 : i_out_dig_1) :
(dac2mux[0] ? q_out_dig_0 : i_out_dig_0));
+ wire tx_dig_b_b = (dac3mux[1] ? (dac3mux[0] ? q_out_dig_1 : i_out_dig_1) :
(dac3mux[0] ? q_out_dig_0 : i_out_dig_0));
+
+ //wire [1:0] tx_dig_a = {tx_dig_a_a,tx_dig_b_a};
+ //wire [1:0] tx_dig_b = {tx_dig_a_b,tx_dig_b_b};
+
+ //wire tx_dig_a_chan = (dac0mux[1] | dac1mux[1] );
+ //wire tx_dig_b_chan = (dac2mux[1] | dac3mux[1] );
+
+ //TODO make enabling tx_dig configurable through register
+
+ wire enable_tx_dig_a = 1'b1 & enable_tx;
+ wire enable_tx_dig_b = 1'b1 & enable_tx;
+
+ wire tx_dig_a_a_en = dac0mux[3] & enable_tx_dig_a;
+ wire tx_dig_b_a_en = dac1mux[3] & enable_tx_dig_a;
+ wire tx_dig_a_b_en = dac2mux[3] & enable_tx_dig_b;
+ wire tx_dig_b_b_en = dac3mux[3] & enable_tx_dig_b;
+
+ //TODO make gpio bits used for tx_dig configurable through register
+ assign io_tx_a_out =
{tx_dig_a_a_en?tx_dig_a_a:reg_0[15],tx_dig_b_a_en?tx_dig_b_a:reg_0[14],reg_0[13:0]};
+ assign io_tx_b_out =
{tx_dig_a_b_en?tx_dig_a_b:reg_2[15],tx_dig_b_b_en?tx_dig_b_b:reg_2[14],reg_2[13:0]};
+ assign io_tx_a_force_output = {tx_dig_a_a_en,tx_dig_b_a_en,14'b0};
+ assign io_tx_b_force_output = {tx_dig_a_b_en,tx_dig_b_b_en,14'b0};
+
+
+ `ifdef TX_EN_DIG_0
+ //TODO make enabling tx_dig configurable through register
+ //tx_chain_dig tx_chain_dig_0
+ // ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ // .i_in(ch0tx), q_in(ch1tx),
+ // .i_out_ana(bb_tx_i0),
+ // .q_out_ana(bb_tx_q0),
+ // .i_out_dig(i_out_dig_0),
+ // .q_out_dig(q_out_dig_0)
+ // );
+ tx_chain_dig tx_chain_dig_0
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ .i_in(ch0tx),.q_in(ch1tx),
+ .i_out_ana(bb_tx_i0),.q_out_ana(bb_tx_q0),
+ .i_out_dig(i_out_dig_0),.q_out_dig(q_out_dig_0));
+ `else
+ assign bb_tx_i0 = ch0tx;
+ assign bb_tx_q0 = ch1tx;
+ assign i_out_dig_0=1'b0;
+ assign q_out_dig_0=1'b0;
+ `endif
+
+ `ifdef TX_EN_DIG_1
+ //TODO make enabling tx_dig configurable through register
+ tx_chain_dig tx_chain_dig_1
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ .i_in(ch2tx),.q_in(ch3tx),
+ .i_out_ana(bb_tx_i1),.q_out_ana(bb_tx_q1),
+ .i_out_dig(i_out_dig_1),.q_out_dig(q_out_dig_1));
+// tx_chain_dig tx_chain_dig_1
+// ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+// .i_in(ch2tx), q_in(ch3tx),
+// .i_out_ana(bb_tx_i1),
+// .q_out_ana(bb_tx_q1),
+// .i_out_dig(i_out_dig_1),
+// .q_out_dig(q_out_dig_1)
+// );
+ `else
+ assign bb_tx_i1 = ch2tx;
+ assign bb_tx_q1 = ch3tx;
+ assign i_out_dig_1=1'b0;
+ assign q_out_dig_1=1'b0;
+ `endif
+
+ wire txsync = tx_sample_strobe;
+ assign TXSYNC_A = txsync;
+ assign TXSYNC_B = txsync;
+
+ assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
+ assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
+`else // `ifdef TX_ON
+ assign io_tx_a_out = reg_0;
+ assign io_tx_b_out = reg_2;
+ assign io_tx_a_force_output=16'b0;
+ assign io_tx_b_force_output=16'b0;
+`endif
+
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Receive Side
+`ifdef RX_ON
+ wire rx_sample_strobe,strobe_decim,hb_strobe;
+ wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
+ bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
+
+ wire loopback = settings[0];
+ wire counter = settings[1];
+
+ always @(posedge clk64)
+ if(rx_dsp_reset)
+ debug_counter <= #1 16'd0;
+ else if(~enable_rx)
+ debug_counter <= #1 16'd0;
+ else if(hb_strobe)
+ debug_counter <=#1 debug_counter + 16'd2;
+
+ always @(posedge clk64)
+ if(strobe_interp)
+ begin
+ loopback_i_0 <= #1 ch0tx;
+ loopback_q_0 <= #1 ch1tx;
+ end
+
+
+ wire [15:0]
ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
+ wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
+
+ adc_interface
adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
+
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
+ .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
+ .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
+ .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
+
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
+
+ rx_buffer rx_buffer
+ ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
+ .reset_regs(rx_dsp_reset),
+
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+ .channels(rx_numchan),
+ .ch_0(ch0rx_ext),.ch_1(ch1rx_ext),
+ .ch_2(ch2rx),.ch_3(ch3rx),
+ .ch_4(ch4rx),.ch_5(ch5rx),
+ .ch_6(ch6rx),.ch_7(ch7rx),
+ .rxclk(clk64),.rxstrobe(hb_strobe),
+ .clear_status(clear_status),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .debugbus(rx_debugbus) );
+
+ `ifdef RX_EN_0
+ rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
+ ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
+
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
+ `else
+ assign bb_rx_i0=16'd0;
+ assign bb_rx_q0=16'd0;
+ `endif
+
+ `ifdef RX_EN_1
+ rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
+ ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
+
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
+ `else
+ assign bb_rx_i1=16'd0;
+ assign bb_rx_q1=16'd0;
+ `endif
+
+ `ifdef RX_EN_2
+ rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
+ ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
+
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
+ `else
+ assign bb_rx_i2=16'd0;
+ assign bb_rx_q2=16'd0;
+ `endif
+
+ `ifdef RX_EN_3
+ rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
+ ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
+
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
+ `else
+ assign bb_rx_i3=16'd0;
+ assign bb_rx_q3=16'd0;
+ `endif
+
+ `ifdef RX_DIG_ON
+ wire enable_rx_dig = 1'b1 & enable_rx;//TODO make enabling rx_dig
configurable through register
+ assign io_rx_a_force_input = {enable_rx_dig,enable_rx_dig,14'b0};
+ assign io_rx_b_force_input = {enable_rx_dig,enable_rx_dig,14'b0};
+ gpio_input gpio_input(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
+ .out_strobe(hb_strobe),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .io_rx_a_in(io_rx_a),.io_rx_b_in(io_rx_b),
+ //.io_tx_a_in(io_tx_a),.io_tx_b_in(io_tx_b),
+ .rx_dig0_i(rx_dig0_i),.rx_dig0_q(rx_dig0_q),
+ .rx_dig1_i(rx_dig1_i),.rx_dig1_q(rx_dig1_q) );
+
+ `ifdef RX_EN_DIG_0
+ rx_chain_dig rx_chain_dig_0
+ ( .clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx_dig),
+ .i_in_ana(bb_rx_i0),.q_in_ana(bb_rx_q0),
+ .i_in_dig(rx_dig0_i),.q_in_dig(rx_dig0_q),
+ .i_out(ch0rx),.q_out(ch1rx));
+ `else
+ assign ch0rx = bb_rx_i0;
+ assign ch1rx = bb_rx_q0;
+ `endif
+
+ assign ch0rx_ext = counter ? debug_counter : loopback ? loopback_i_0 :
ch0rx;
+ assign ch1rx_ext = counter ? debug_counter + 16'd1 : loopback ?
loopback_q_0 : ch1rx;
+
+ `ifdef RX_EN_DIG_1
+ rx_chain_dig rx_chain_dig_1
+ ( .clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx_dig),
+ .i_in_ana(bb_rx_i1),.q_in_ana(bb_rx_q1),
+ .i_in_dig(rx_dig1_i),.q_in_dig(rx_dig1_q),
+ .i_out(ch2rx),.q_out(ch3rx));
+ `else
+ assign ch2rx = bb_rx_i1;
+ assign ch3rx = bb_rx_q1;
+ `endif
+
+ assign ch4rx = bb_rx_i2;
+ assign ch5rx = bb_rx_q2;
+ assign ch6rx = bb_rx_i3;
+ assign ch7rx = bb_rx_q3;
+ `else // `ifdef RX_DIG_ON
+ assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
+ assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 :
bb_rx_q0;
+ assign ch2rx = bb_rx_i1;
+ assign ch3rx = bb_rx_q1;
+ assign ch4rx = bb_rx_i2;
+ assign ch5rx = bb_rx_q2;
+ assign ch6rx = bb_rx_i3;
+ assign ch7rx = bb_rx_q3;
+ `endif // `ifdef RX_DIG_ON
+
+`endif // `ifdef RX_ON
+
+
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Control Functions
+
+ wire [31:0] capabilities;
+ assign capabilities[7] = `TX_CAP_HB;
+ assign capabilities[6:4] = `TX_CAP_NCHAN;
+ assign capabilities[3] = `RX_CAP_HB;
+ assign capabilities[2:0] = `RX_CAP_NCHAN;
+
+
+ serial_io serial_io
+ ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
+ .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
+
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
+ );
+
+ wire [15:0] reg_0,reg_1,reg_2,reg_3;
+ wire [15:0] io_tx_a_out;
+ wire [15:0] io_tx_b_out;
+ wire [15:0] io_tx_a_force_output;
+ wire [15:0] io_tx_b_force_output;
+ wire [15:0] io_rx_a_force_input;
+ wire [15:0] io_rx_b_force_input;
+
+ master_control master_control
+ ( .master_clk(clk64),.usbclk(usbclk),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+ .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+ .enable_tx(enable_tx),.enable_rx(enable_rx),
+ .interp_rate(interp_rate),.decim_rate(decim_rate),
+ .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+ .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+ .tx_empty(tx_empty),
+ //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
+ .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]),
+ .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]),
+ //.tx_dig_a(tx_dig_a),tx_dig_b(tx_dig_b),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+
+ io_pins io_pins
+ (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
+ .reg_0(io_tx_a_out),.reg_1(reg_1),.reg_2(io_tx_b_out),.reg_3(reg_3),
+ .io_0_force_output(io_tx_a_force_output),
.io_2_force_output(io_tx_b_force_output),
+ .io_1_force_input(io_rx_a_force_input),
.io_3_force_input(io_rx_b_force_input),
+ .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+
+
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Misc Settings
+ setting_reg #(`FR_MODE)
sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
+
+endmodule // usrp_gpio
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/lib (from rev 7618,
gnuradio/trunk/gr-gpio/src/lib)
Property changes on: gnuradio/branches/releases/3.1/gr-gpio/src/lib
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
.deps
.libs
*.pyc
gpio_swig*
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/lib/Makefile.am
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/lib/Makefile.am (from rev
7618, gnuradio/trunk/gr-gpio/src/lib/Makefile.am)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/lib/Makefile.am
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/lib/Makefile.am 2008-02-24
19:07:53 UTC (rev 7817)
@@ -0,0 +1,87 @@
+#
+# Copyright 2004,2005,2006,2007,2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+include $(top_srcdir)/Makefile.common
+
+ourpythondir = $(grpythondir)/gpio
+ourlibdir = $(grpyexecdir)/gpio
+
+INCLUDES = $(STD_DEFINES_AND_INCLUDES) $(PYTHON_CPPFLAGS) $(WITH_INCLUDES)
+
+SWIGPYTHONARGS = $(SWIGPYTHONFLAGS) $(STD_DEFINES_AND_INCLUDES) \
+ $(WITH_SWIG_INCLUDES) $(WITH_INCLUDES)
+
+ALL_IFILES = \
+ $(LOCAL_IFILES) \
+ $(NON_LOCAL_IFILES)
+
+NON_LOCAL_IFILES = $(GNURADIO_I)
+
+LOCAL_IFILES = \
+ $(top_srcdir)/gr-gpio/src/lib/gpio.i
+
+# These files are built by SWIG. The first is the C++ glue.
+# The second is the python wrapper that loads the _gpio shared library
+# and knows how to call our extensions.
+
+BUILT_SOURCES = \
+ gpio_swig.cc \
+ gpio_swig.py
+
+# This gets gpio.py installed in the right place
+ourpython_PYTHON = \
+ gpio_swig.py
+
+ourlib_LTLIBRARIES = _gpio_swig.la
+
+# These are the source files that go into the shared library
+_gpio_swig_la_SOURCES = \
+ gpio_swig.cc \
+ gpio_and_const_ss.cc
+
+# magic flags
+_gpio_swig_la_LDFLAGS = $(NO_UNDEFINED) -module -avoid-version
+
+# link the library against some comon swig runtime code and the
+# c++ standard library
+_gpio_swig_la_LIBADD = \
+ $(PYTHON_LDFLAGS) \
+ $(GNURADIO_CORE_LA) \
+ -lstdc++
+
+gpio_swig.cc gpio_swig.py: $(LOCAL_IFILES) $(ALL_IFILES)
+ $(SWIG) $(SWIGPYTHONARGS) -module gpio_swig -o gpio_swig.cc
$(LOCAL_IFILES)
+
+# These headers get installed in ${prefix}/include/gnuradio
+grinclude_HEADERS = \
+ gpio_and_const_ss.h
+
+# These swig headers get installed in ${prefix}/include/gnuradio/swig
+swiginclude_HEADERS = \
+ $(LOCAL_IFILES)
+
+
+# Don't distribute output of swig
+dist-hook:
+ @for file in $(BUILT_SOURCES); do echo $(RM) $(distdir)/$$file; done
+ @for file in $(BUILT_SOURCES); do $(RM) $(distdir)/$$file; done
+
+MOSTLYCLEANFILES = $(BUILT_SOURCES) *.pyc *~
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio.i
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio.i (from rev 7618,
gnuradio/trunk/gr-gpio/src/lib/gpio.i)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio.i
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio.i 2008-02-24
19:07:53 UTC (rev 7817)
@@ -0,0 +1,28 @@
+/* -*- c++ -*- */
+
+%feature("autodoc", "1"); // generate python docstrings
+
+%include "exception.i"
+%import "gnuradio.i" // the common stuff
+
+%{
+#include "gnuradio_swig_bug_workaround.h" // mandatory bug fix
+#include "gpio_and_const_ss.h"
+#include <stdexcept>
+%}
+
+// ----------------------------------------------------------------
+
+GR_SWIG_BLOCK_MAGIC(gpio,and_const_ss)
+
+gpio_and_const_ss_sptr gpio_make_and_const_ss (unsigned short k);
+
+class gpio_and_const_ss : public gr_sync_block
+{
+ private:
+ gpio_and_const_ss (unsigned short k);
+
+ public:
+ unsigned short k () const { return d_k; }
+ void set_k (unsigned short k) { d_k = k; }
+};
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.cc
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.cc
(from rev 7618, gnuradio/trunk/gr-gpio/src/lib/gpio_and_const_ss.cc)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.cc
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.cc
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,71 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <gpio_and_const_ss.h>
+#include <gr_io_signature.h>
+
+gpio_and_const_ss_sptr
+gpio_make_and_const_ss (unsigned short k)
+{
+ return gpio_and_const_ss_sptr (new gpio_and_const_ss (k));
+}
+
+gpio_and_const_ss::gpio_and_const_ss (unsigned short k)
+ : gr_sync_block ("and_const_ss",
+ gr_make_io_signature (1, 1, sizeof (short)),
+ gr_make_io_signature (1, 1, sizeof (short))),
+ d_k (k)
+{
+}
+
+int
+gpio_and_const_ss::work (int noutput_items,
+ gr_vector_const_void_star &input_items,
+ gr_vector_void_star &output_items)
+{
+ short *iptr = (short *) input_items[0];
+ short *optr = (short *) output_items[0];
+
+ int size = noutput_items;
+
+ while (size >= 8){
+ *optr++ = *iptr++ & d_k;
+ *optr++ = *iptr++ & d_k;
+ *optr++ = *iptr++ & d_k;
+ *optr++ = *iptr++ & d_k;
+ *optr++ = *iptr++ & d_k;
+ *optr++ = *iptr++ & d_k;
+ *optr++ = *iptr++ & d_k;
+ *optr++ = *iptr++ & d_k;
+ size -= 8;
+ }
+
+ while (size-- > 0)
+ *optr++ = *iptr++ & d_k;
+
+ return noutput_items;
+}
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.h
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.h
(from rev 7618, gnuradio/trunk/gr-gpio/src/lib/gpio_and_const_ss.h)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.h
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/lib/gpio_and_const_ss.h
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,54 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifndef INCLUDED_GPIO_AND_CONST_SS_H
+#define INCLUDED_GPIO_AND_CONST_SS_H
+
+#include <gr_sync_block.h>
+
+class gpio_and_const_ss;
+typedef boost::shared_ptr<gpio_and_const_ss> gpio_and_const_ss_sptr;
+
+gpio_and_const_ss_sptr gpio_make_and_const_ss (unsigned short k);
+
+/*!
+ * \brief output = input & constant
+ * \ingroup block
+ */
+class gpio_and_const_ss : public gr_sync_block
+{
+ friend gpio_and_const_ss_sptr gpio_make_and_const_ss (unsigned short k);
+
+ unsigned short d_k; // the constant
+ gpio_and_const_ss (unsigned short k);
+
+ public:
+ unsigned short k () const { return d_k; }
+ void set_k (unsigned short k) { d_k = k; }
+
+ int work (int noutput_items,
+ gr_vector_const_void_star &input_items,
+ gr_vector_void_star &output_items);
+};
+
+#endif
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python (from rev 7618,
gnuradio/trunk/gr-gpio/src/python)
Property changes on: gnuradio/branches/releases/3.1/gr-gpio/src/python
___________________________________________________________________
Name: svn:ignore
+ Makefile
Makefile.in
*.pyc
run_tests
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/python/Makefile.am
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python/Makefile.am (from rev
7618, gnuradio/trunk/gr-gpio/src/python/Makefile.am)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/python/Makefile.am
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/python/Makefile.am
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,50 @@
+#
+# Copyright 2007,2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+include $(top_srcdir)/Makefile.common
+
+# Installation locations
+ourpythondir = $(grpythondir)/gpio
+ourlibdir = $(grpyexecdir)/gpio
+
+# List of Python files that will get installed into site-packages
+ourpython_PYTHON = \
+ __init__.py \
+ gpio.py
+
+# List of python files that will be installed onto $prefix/bin
+bin_SCRIPTS = \
+ gpio_rx_sfile.py \
+ gpio_usrp_siggen.py \
+ gpio_usrp_fft.py
+
+# List of python files that will get distributed in tarball
+# but not installed anywhere on system
+noinst_PYTHON = \
+ qa_gpio.py
+
+# Programs that get run by 'make check'
+TESTS = run_tests
+
+# Files to go into tarball not otherwise mentioned (except bin_SCRIPTS!)
+EXTRA_DIST = run_tests.in $(bin_SCRIPTS)
+
+MOSTLYCLEANFILES = *.pyo *.pyc *~
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/python/__init__.py
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python/__init__.py (from rev
7618, gnuradio/trunk/gr-gpio/src/python/__init__.py)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/python/__init__.py
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/python/__init__.py
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,34 @@
+#
+# Copyright 2007,2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+import glob
+import os.path
+
+# This automatically imports all top-level objects from .py files
+# in our directory into the package name space
+for _p in __path__:
+ _filenames = glob.glob (os.path.join (_p, "*.py"))
+ for _f in _filenames:
+ _f = os.path.basename(_f).lower()
+ _f = _f[:-3]
+ if _f == '__init__':
+ continue
+ exec "from %s import *" % (_f,)
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio.py
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio.py (from rev
7618, gnuradio/trunk/gr-gpio/src/python/gpio.py)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio.py
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio.py 2008-02-24
19:07:53 UTC (rev 7817)
@@ -0,0 +1,3 @@
+from gpio_swig import *
+
+fpga_filename = 'usrp_gpio.rbf'
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_rx_sfile.py
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_rx_sfile.py
(from rev 7618, gnuradio/trunk/gr-gpio/src/python/gpio_rx_sfile.py)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_rx_sfile.py
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_rx_sfile.py
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,121 @@
+#!/usr/bin/env python
+#
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+from gnuradio import gr, eng_notation
+from gnuradio import usrp
+from gnuradio.eng_option import eng_option
+from optparse import OptionParser
+import sys
+
+from gnuradio import gpio
+
+class my_top_block(gr.top_block):
+
+ def __init__(self, options):
+ gr.top_block.__init__(self)
+
+ # Create a USRP source with GPIO FPGA build, then configure
+ u =
usrp.source_s(decim_rate=options.decim,fpga_filename=gpio.fpga_filename)
+
+ if options.force_complex_RXA:
+ # This is a dirty hack to force complex mode (receive both I and Q)
on basicRX or LFRX
+ # This forces the receive board in RXA (side A) to be used
+ # FIXME: This has as a side effect that the gain for Q is not set.
So only use with gain 0 (--gain 0)
+ options.rx_subdev_spec=(0,0)
+ u.set_mux(0x10)
+ if not (0==options.gain):
+ print "WARNING, you should set the gain to 0 with --gain 0 when
using --force-complex-RXA"
+ print "The gain for Q will now still be zero while the gain for I
is not"
+ #options.gain=0
+ else:
+ if options.rx_subdev_spec is None:
+ options.rx_subdev_spec = usrp.pick_rx_subdevice(u)
+ u.set_mux(usrp.determine_rx_mux_value(u, options.rx_subdev_spec))
+
+ subdev = usrp.selected_subdev(u, options.rx_subdev_spec)
+ print "Using RX d'board %s" % (subdev.side_and_name(),)
+ input_rate = u.adc_freq()/u.decim_rate()
+ print "USB sample rate %s" % (eng_notation.num_to_str(input_rate))
+
+ if options.gain is None:
+ # if no gain was specified, use the mid-point in dB
+ g = subdev.gain_range()
+ options.gain = float(g[0]+g[1])/2
+
+
+ #TODO setting gain on basicRX only sets the I channel, use a second
subdev to set gain of Q channel
+ #see gnuradio-examples/multi-antenna for possible solutions
+ subdev.set_gain(options.gain)
+
+ #TODO check if freq has same problem as gain when trying to use
complex mode on basicRX
+ r = u.tune(0, subdev, options.freq)
+ if not r:
+ sys.stderr.write('Failed to set frequency\n')
+ raise SystemExit, 1
+
+ # Connect pipeline
+ src = u
+ if options.nsamples is not None:
+ head = gr.head(gr.sizeof_short, int(options.nsamples)*2)
+ self.connect(u, head)
+ src = head
+
+ ana_strip = gpio.and_const_ss(0xFFFE)
+ dig_strip = gpio.and_const_ss(0x0001)
+ ana_sink = gr.file_sink(gr.sizeof_short, options.ana_filename)
+ dig_sink = gr.file_sink(gr.sizeof_short, options.dig_filename)
+
+ self.connect(src, ana_strip, ana_sink)
+ self.connect(src, dig_strip, dig_sink)
+
+if __name__ == '__main__':
+ usage="%prog: [options] analog_filename digital_filename"
+ parser = OptionParser(option_class=eng_option, usage=usage)
+ parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=(0, 0),
+ help="select USRP Rx side A or B (default=A)")
+ parser.add_option("-d", "--decim", type="int", default=16,
+ help="set fgpa decimation rate to DECIM
[default=%default]")
+ parser.add_option("-f", "--freq", type="eng_float", default=None,
+ help="set frequency to FREQ", metavar="FREQ")
+ parser.add_option("-g", "--gain", type="eng_float", default=None,
+ help="set gain in dB (default is midpoint)")
+ parser.add_option("-N", "--nsamples", type="eng_float", default=None,
+ help="number of samples to collect [default=+inf]")
+ parser.add_option("-F", "--force-complex-RXA", action="store_true",
default=False,
+ help="enable basicRX hack to force complex mode on
basicRX and LFRX. Only works on side A. Only use with --gain 0")
+ (options, args) = parser.parse_args ()
+ if len(args) != 2:
+ parser.print_help()
+ raise SystemExit, 1
+ options.ana_filename = args[0]
+ options.dig_filename = args[1]
+
+ if options.freq is None:
+ parser.print_help()
+ sys.stderr.write('You must specify the frequency with -f FREQ\n');
+ raise SystemExit, 1
+
+ try:
+ tb = my_top_block(options)
+ tb.run()
+ except KeyboardInterrupt:
+ pass
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_fft.py
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_fft.py
(from rev 7618, gnuradio/trunk/gr-gpio/src/python/gpio_usrp_fft.py)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_fft.py
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_fft.py
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,333 @@
+#!/usr/bin/env python
+#
+# Copyright 2004,2005,2007,2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+from gnuradio import gr, gru
+from gnuradio import usrp
+from gnuradio import eng_notation
+from gnuradio.eng_option import eng_option
+from gnuradio.wxgui import stdgui2, fftsink2, waterfallsink2, scopesink2,
form, slider
+from optparse import OptionParser
+import wx
+import sys
+import numpy
+
+from gnuradio import gpio
+
+def pick_subdevice(u):
+ """
+ The user didn't specify a subdevice on the command line.
+ If there's a daughterboard on A, select A.
+ If there's a daughterboard on B, select B.
+ Otherwise, select A.
+ """
+ if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a
problem
+ return (0, 0)
+ #if u.db[1][0].dbid() >= 0: #disable the use of RXB
+ # return (1, 0)
+ return (0, 0)
+
+
+class app_top_block(stdgui2.std_top_block):
+ def __init__(self, frame, panel, vbox, argv):
+ stdgui2.std_top_block.__init__(self, frame, panel, vbox, argv)
+
+ self.frame = frame
+ self.panel = panel
+
+ parser = OptionParser(option_class=eng_option)
+ parser.add_option("-w", "--which", type="int", default=0,
+ help="select which USRP (0, 1, ...) default is
%default",
+ metavar="NUM")
+# parser.add_option("-R", "--rx-subdev-spec", type="subdev",
default=None,
+# help="select USRP Rx side A or B (default=first one
with a daughterboard)")
+ parser.add_option("-A", "--antenna", default=None,
+ help="select Rx Antenna (only on RFX-series boards)")
+ parser.add_option("-d", "--decim", type="int", default=32,
+ help="set fgpa decimation rate to DECIM
[default=%default]")
+ parser.add_option("-f", "--freq", type="eng_float", default=0.0,
+ help="set frequency to FREQ", metavar="FREQ")
+ parser.add_option("-g", "--gain", type="eng_float", default=None,
+ help="set gain in dB (default is midpoint)")
+ parser.add_option("-W", "--waterfall", action="store_true",
default=False,
+ help="Enable waterfall display")
+ parser.add_option("-8", "--width-8", action="store_true",
default=False,
+ help="Enable 8-bit samples across USB")
+# parser.add_option( "--no-hb", action="store_true", default=False,
+# help="don't use halfband filter in usrp")
+ parser.add_option("-S", "--oscilloscope", action="store_true",
default=False,
+ help="Enable oscilloscope display (default)")
+ parser.add_option("-F", "--fft", action="store_true", default=False,
+ help="Enable FFT display")
+ parser.add_option("-n", "--frame-decim", type="int", default=1,
+ help="set oscope frame decimation factor to n
[default=1]")
+ parser.add_option("-v", "--v-scale", type="eng_float", default=1,
+ help="set oscope initial V/div to SCALE
[default=%default]")
+ parser.add_option("-t", "--t-scale", type="eng_float", default=10e-6,
+ help="set oscope initial s/div to SCALE
[default=10us]")
+ parser.add_option ("--digital", action="store_true", default=False,
+ help="show (only) the digital wave on lsb (will be
input from gpio pins with special usrp firmware)")
+ parser.add_option ("--analog", action="store_true", default=False,
+ help="show (only) the analog wave on msbs (will be
input from analog inputs)")
+ parser.add_option ("--file", default=None,
+ help="input from file FILE in stead of USRP (will be
input from raw file in interleaved short format)")
+ (options, args) = parser.parse_args()
+ if len(args) != 0:
+ parser.print_help()
+ sys.exit(1)
+ self.options = options
+ self.show_debug_info = True
+
+ self.u = usrp.source_s(which=options.which, decim_rate=options.decim,
fpga_filename=gpio.fpga_filename)
+
+ print "Warning: This script only supports boards on RXA, change the
script if you want otherwise"
+ #options.rx_subdev_spec=(0, 0)#force the use of RXA
+ options.rx_subdev_spec=None #force the use of RXA
+
+ if options.rx_subdev_spec is None:
+ options.rx_subdev_spec = pick_subdevice(self.u)
+
+ #This hardcoded mux setting is why this script only supports RXA
+ #We want both I and Q active, even when using basicRX
+ #set to 0x10 for RXA
+ #set to 0x32 for RXB
+ self.u.set_mux(0x10) #usrp.determine_rx_mux_value(self.u,
options.rx_subdev_spec))
+
+ if options.width_8:
+ width = 8
+ shift = 8
+ format = self.u.make_format(width, shift)
+ print "format =", hex(format)
+ r = self.u.set_format(format)
+ print "set_format =", r
+
+ # determine the daughterboard subdevice we're using
+ self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec)
+ #if options.rx_subdev_spec==(0,0):
+ # rx_subdev_spec2=(0,1)
+ # self.subdev2 = usrp.selected_subdev(self.u, rx_subdev_spec2)
+ input_rate = self.u.adc_freq() / self.u.decim_rate()
+
+ if options.waterfall:
+ self.scope = \
+ waterfallsink2.waterfall_sink_c (panel, fft_size=1024,
sample_rate=input_rate)
+ elif options.fft:
+ self.scope = fftsink2.fft_sink_c (panel, fft_size=1024,
sample_rate=input_rate)
+ else: # options.oscilloscope:
+ #self.scope = scopesink2.scope_sink_c(panel,
sample_rate=input_rate)
+ self.scope = scopesink2.scope_sink_c(panel, sample_rate=input_rate,
+ frame_decim=options.frame_decim,
+ v_scale=options.v_scale,
+ t_scale=options.t_scale)
+
+ self.is2c = gr.interleaved_short_to_complex()
+ if not (options.file is None):
+ self.filesrc=gr.file_source(gr.sizeof_short, options.file, True)
+ thr = gr.throttle(gr.sizeof_short, input_rate)
+ self.connect(self.filesrc,thr,self.is2c,self.scope)
+ elif options.digital:
+ self.select_dig=gpio.and_const_ss(0x0001)
+ self.connect(self.u, self.select_dig,self.is2c,self.scope)
+ elif options.analog:
+ self.select_ana=gpio.and_const_ss(0xFFFE)
+ self.connect(self.u, self.select_ana,self.is2c,self.scope)
+ else:
+ self.connect(self.u,self.is2c,self.scope)
+
+ self._build_gui(vbox)
+ self._setup_events()
+
+ # set initial values
+
+ if options.gain is None:
+ # if no gain was specified, use the mid-point in dB
+ g = self.subdev.gain_range()
+ options.gain = float(g[0]+g[1])/2
+
+ if options.freq is None:
+ # if no freq was specified, use the mid-point
+ r = self.subdev.freq_range()
+ options.freq = float(r[0]+r[1])/2
+
+ self.set_gain(options.gain)
+
+ if options.antenna is not None:
+ print "Selecting antenna %s" % (options.antenna,)
+ self.subdev.select_rx_antenna(options.antenna)
+
+ if self.show_debug_info:
+ self.myform['decim'].set_value(self.u.decim_rate())
+ self.myform['address@hidden'].set_value(self.u.adc_freq() /
self.u.decim_rate())
+ self.myform['dbname'].set_value(self.subdev.name())
+ self.myform['baseband'].set_value(0)
+ self.myform['ddc'].set_value(0)
+
+ if not(self.set_freq(options.freq)):
+ self._set_status_msg("Failed to set initial frequency")
+
+ def _set_status_msg(self, msg):
+ self.frame.GetStatusBar().SetStatusText(msg, 0)
+
+ def _build_gui(self, vbox):
+
+ def _form_set_freq(kv):
+ return self.set_freq(kv['freq'])
+
+ vbox.Add(self.scope.win, 10, wx.EXPAND)
+
+ # add control area at the bottom
+ self.myform = myform = form.form()
+ hbox = wx.BoxSizer(wx.HORIZONTAL)
+ hbox.Add((5,0), 0, 0)
+ myform['freq'] = form.float_field(
+ parent=self.panel, sizer=hbox, label="Center freq", weight=1,
+ callback=myform.check_input_and_call(_form_set_freq,
self._set_status_msg))
+
+ hbox.Add((5,0), 0, 0)
+ g = self.subdev.gain_range()
+ myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox,
label="Gain",
+ weight=3,
+ min=int(g[0]), max=int(g[1]),
+ callback=self.set_gain)
+
+ hbox.Add((5,0), 0, 0)
+ vbox.Add(hbox, 0, wx.EXPAND)
+
+ self._build_subpanel(vbox)
+
+ def _build_subpanel(self, vbox_arg):
+ # build a secondary information panel (sometimes hidden)
+
+ # FIXME figure out how to have this be a subpanel that is always
+ # created, but has its visibility controlled by foo.Show(True/False)
+
+ def _form_set_decim(kv):
+ return self.set_decim(kv['decim'])
+
+ if not(self.show_debug_info):
+ return
+
+ panel = self.panel
+ vbox = vbox_arg
+ myform = self.myform
+
+ #panel = wx.Panel(self.panel, -1)
+ #vbox = wx.BoxSizer(wx.VERTICAL)
+
+ hbox = wx.BoxSizer(wx.HORIZONTAL)
+ hbox.Add((5,0), 0)
+
+ myform['decim'] = form.int_field(
+ parent=panel, sizer=hbox, label="Decim",
+ callback=myform.check_input_and_call(_form_set_decim,
self._set_status_msg))
+
+ hbox.Add((5,0), 1)
+ myform['address@hidden'] = form.static_float_field(
+ parent=panel, sizer=hbox, label="address@hidden")
+
+ hbox.Add((5,0), 1)
+ myform['dbname'] = form.static_text_field(
+ parent=panel, sizer=hbox)
+
+ hbox.Add((5,0), 1)
+ myform['baseband'] = form.static_float_field(
+ parent=panel, sizer=hbox, label="Analog BB")
+
+ hbox.Add((5,0), 1)
+ myform['ddc'] = form.static_float_field(
+ parent=panel, sizer=hbox, label="DDC")
+
+ hbox.Add((5,0), 0)
+ vbox.Add(hbox, 0, wx.EXPAND)
+
+
+ def set_freq(self, target_freq):
+ """
+ Set the center frequency we're interested in.
+
+ @param target_freq: frequency in Hz
+ @rypte: bool
+
+ Tuning is a two step process. First we ask the front-end to
+ tune as close to the desired frequency as it can. Then we use
+ the result of that operation and our target_frequency to
+ determine the value for the digital down converter.
+ """
+ r = self.u.tune(0, self.subdev, target_freq)
+
+ if r:
+ self.myform['freq'].set_value(target_freq) # update displayed
value
+ if self.show_debug_info:
+ self.myform['baseband'].set_value(r.baseband_freq)
+ self.myform['ddc'].set_value(r.dxc_freq)
+ if not self.options.waterfall and not self.options.oscilloscope:
+ self.scope.win.set_baseband_freq(target_freq)
+ return True
+
+ return False
+
+ def set_gain(self, gain):
+ self.myform['gain'].set_value(gain) # update displayed value
+ self.subdev.set_gain(gain)
+
+ def set_decim(self, decim):
+ ok = self.u.set_decim_rate(decim)
+ if not ok:
+ print "set_decim failed"
+ input_rate = self.u.adc_freq() / self.u.decim_rate()
+ self.scope.set_sample_rate(input_rate)
+ if self.show_debug_info: # update displayed values
+ self.myform['decim'].set_value(self.u.decim_rate())
+ self.myform['address@hidden'].set_value(self.u.adc_freq() /
self.u.decim_rate())
+ return ok
+
+ def _setup_events(self):
+ if not self.options.waterfall and not self.options.oscilloscope:
+ self.scope.win.Bind(wx.EVT_LEFT_DCLICK, self.evt_left_dclick)
+
+ def evt_left_dclick(self, event):
+ (ux, uy) = self.scope.win.GetXY(event)
+ if event.CmdDown():
+ # Re-center on maximum power
+ points = self.scope.win._points
+ if self.scope.win.peak_hold:
+ if self.scope.win.peak_vals is not None:
+ ind = numpy.argmax(self.scope.win.peak_vals)
+ else:
+ ind = int(points.shape()[0]/2)
+ else:
+ ind = numpy.argmax(points[:,1])
+ (freq, pwr) = points[ind]
+ target_freq = freq/self.scope.win._scale_factor
+ print ind, freq, pwr
+ self.set_freq(target_freq)
+ else:
+ # Re-center on clicked frequency
+ target_freq = ux/self.scope.win._scale_factor
+ self.set_freq(target_freq)
+
+
+def main ():
+ app = stdgui2.stdapp(app_top_block, "USRP FFT", nstatus=1)
+ app.MainLoop()
+
+if __name__ == '__main__':
+ main ()
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_siggen.py
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_siggen.py
(from rev 7618, gnuradio/trunk/gr-gpio/src/python/gpio_usrp_siggen.py)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_siggen.py
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/python/gpio_usrp_siggen.py
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,209 @@
+#!/usr/bin/env python
+#
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+from gnuradio import gr, gru
+from gnuradio import usrp
+from gnuradio.eng_option import eng_option
+from gnuradio import eng_notation
+from optparse import OptionParser
+import sys
+
+from gnuradio import gpio
+
+class my_top_block(gr.top_block):
+ def __init__ (self):
+ gr.top_block.__init__(self)
+
+ # controllable values
+ self.interp = 64
+ self.waveform_type = gr.GR_CONST_WAVE
+ self.waveform_ampl = 16000
+ self.waveform_freq = 100.12345e3
+ self.waveform_offset = 0
+ self._instantiate_blocks ()
+ self.set_waveform_type (self.waveform_type)
+
+ def usb_freq (self):
+ return self.u.dac_freq() / self.interp
+
+ def usb_throughput (self):
+ return self.usb_freq () * 4
+
+ def set_waveform_type (self, type):
+ '''
+ valid waveform types are: gr.GR_SIN_WAVE, gr.GR_CONST_WAVE,
+ gr.GR_UNIFORM and gr.GR_GAUSSIAN
+ '''
+ self._configure_graph (type)
+ self.waveform_type = type
+
+ def set_waveform_ampl (self, ampl):
+ self.waveform_ampl = ampl
+ self.siggen.set_amplitude (ampl)
+ self.noisegen.set_amplitude (ampl)
+
+ def set_waveform_freq (self, freq):
+ self.waveform_freq = freq
+ self.siggen.set_frequency (freq)
+
+ def set_waveform_offset (self, offset):
+ self.waveform_offset = offset
+ self.siggen.set_offset (offset)
+
+ def set_interpolator (self, interp):
+ self.interp = interp
+ self.siggen.set_sampling_freq (self.usb_freq ())
+ self.u.set_interp_rate (interp)
+
+ def _instantiate_blocks (self):
+ self.src = None
+ self.u = usrp.sink_c (0, self.interp,fpga_filename=gpio.fpga_filename)
+
+ self.siggen = gr.sig_source_c (self.usb_freq (),
+ gr.GR_SIN_WAVE,
+ self.waveform_freq,
+ self.waveform_ampl,
+ self.waveform_offset)
+
+ self.noisegen = gr.noise_source_c (gr.GR_UNIFORM,
+ self.waveform_ampl)
+ self.vecgen = gr.vector_source_c
([complex(1.0,0.0),complex(0.0,0.0),complex(1.0,1.0),complex(0.0,1.0)],True)
+
+ # self.file_sink = gr.file_sink (gr.sizeof_gr_complex, "siggen.dat")
+
+ def _configure_graph (self, type):
+ was_running = self.is_running ()
+ if was_running:
+ self.stop ()
+ self.disconnect_all ()
+ if type == gr.GR_SIN_WAVE:
+ self.connect (self.siggen, self.u)
+ # self.connect (self.siggen, self.file_sink)
+ self.siggen.set_waveform (type)
+ self.src = self.siggen
+ elif type == gr.GR_UNIFORM or type == gr.GR_GAUSSIAN:
+ self.connect (self.noisegen, self.u)
+ self.noisegen.set_type (type)
+ self.src = self.noisegen
+ elif type == gr.GR_CONST_WAVE:
+ self.connect (self.vecgen, self.u)
+ self.src = self.vecgen
+ else:
+ raise ValueError, type
+ if was_running:
+ self.start ()
+
+ def set_freq(self, target_freq):
+ """
+ Set the center frequency we're interested in.
+
+ @param target_freq: frequency in Hz
+ @rypte: bool
+
+ Tuning is a two step process. First we ask the front-end to
+ tune as close to the desired frequency as it can. Then we use
+ the result of that operation and our target_frequency to
+ determine the value for the digital up converter.
+ """
+ r = self.u.tune(self.subdev._which, self.subdev, target_freq)
+ if r:
+ #print "r.baseband_freq =",
eng_notation.num_to_str(r.baseband_freq)
+ #print "r.dxc_freq =", eng_notation.num_to_str(r.dxc_freq)
+ #print "r.residual_freq =",
eng_notation.num_to_str(r.residual_freq)
+ #print "r.inverted =", r.inverted
+ return True
+
+ return False
+
+
+
+def main ():
+ parser = OptionParser (option_class=eng_option)
+ parser.add_option ("-T", "--tx-subdev-spec", type="subdev", default=(0, 0),
+ help="select USRP Tx side A or B")
+ parser.add_option ("-f", "--rf-freq", type="eng_float", default=None,
+ help="set RF center frequency to FREQ")
+ parser.add_option ("-i", "--interp", type="int", default=512,
+ help="set fgpa interpolation rate to INTERP
[default=%default]")
+ parser.add_option ("--sine", dest="type", action="store_const",
const=gr.GR_SIN_WAVE,
+ help="generate a complex sinusoid [default]",
default=gr.GR_SIN_WAVE)
+
+ parser.add_option ("--gaussian", dest="type", action="store_const",
const=gr.GR_GAUSSIAN,
+ help="generate Gaussian random output")
+ parser.add_option ("--uniform", dest="type", action="store_const",
const=gr.GR_UNIFORM,
+ help="generate Uniform random output")
+
+ parser.add_option ("-w", "--waveform-freq", type="eng_float",
default=100e3,
+ help="set waveform frequency to FREQ
[default=%default]")
+ parser.add_option ("-a", "--amplitude", type="eng_float", default=16e3,
+ help="set waveform amplitude to AMPLITUDE
[default=%default]", metavar="AMPL")
+ parser.add_option ("-g", "--gain", type="eng_float", default=None,
+ help="set output gain to GAIN [default=%default]")
+ parser.add_option ("-o", "--offset", type="eng_float", default=0,
+ help="set waveform offset to OFFSET [default=%default]")
+ parser.add_option ("--digital", dest="type", action="store_const",
const=gr.GR_CONST_WAVE,
+ help="generate (only) a digital wave on lsb (will be
output on gpio pins with special usrp firmware)")
+ (options, args) = parser.parse_args ()
+
+ if len(args) != 0:
+ parser.print_help()
+ raise SystemExit
+
+ if options.rf_freq is None:
+ sys.stderr.write("usrp_siggen: must specify RF center frequency with
-f RF_FREQ\n")
+ parser.print_help()
+ raise SystemExit
+
+ tb = my_top_block()
+ tb.set_interpolator (options.interp)
+ tb.set_waveform_type (options.type)
+ tb.set_waveform_freq (options.waveform_freq)
+ tb.set_waveform_ampl (options.amplitude)
+ tb.set_waveform_offset (options.offset)
+
+ # determine the daughterboard subdevice we're using
+ if options.tx_subdev_spec is None:
+ options.tx_subdev_spec = usrp.pick_tx_subdevice(tb.u)
+
+ m = usrp.determine_tx_mux_value(tb.u, options.tx_subdev_spec)
+ #print "mux = %#04x" % (m,)
+ tb.u.set_mux(m)
+ tb.subdev = usrp.selected_subdev(tb.u, options.tx_subdev_spec)
+ print "Using TX d'board %s" % (tb.subdev.side_and_name(),)
+
+ if options.gain is None:
+ tb.subdev.set_gain(tb.subdev.gain_range()[1]) # set max Tx gain
+ else:
+ tb.subdev.set_gain(options.gain) # set max Tx gain
+
+ if not tb.set_freq(options.rf_freq):
+ sys.stderr.write('Failed to set RF frequency\n')
+ raise SystemExit
+
+ tb.subdev.set_enable(True) # enable transmitter
+
+ try:
+ tb.run()
+ except KeyboardInterrupt:
+ pass
+
+if __name__ == '__main__':
+ main ()
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/python/qa_gpio.py
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python/qa_gpio.py (from rev
7618, gnuradio/trunk/gr-gpio/src/python/qa_gpio.py)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/python/qa_gpio.py
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/python/qa_gpio.py
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,36 @@
+#!/usr/bin/env python
+#
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+from gnuradio import gr, gr_unittest
+# This is different from the usage after installation
+import gpio_swig
+
+class qa_gpio (gr_unittest.TestCase):
+
+ def setUp (self):
+ self.tb = gr.top_block()
+
+ def tearDown (self):
+ self.tb = None
+
+if __name__ == '__main__':
+ gr_unittest.main ()
Deleted: gnuradio/branches/releases/3.1/gr-gpio/src/python/run_tests.in
Copied: gnuradio/branches/releases/3.1/gr-gpio/src/python/run_tests.in (from
rev 7618, gnuradio/trunk/gr-gpio/src/python/run_tests.in)
===================================================================
--- gnuradio/branches/releases/3.1/gr-gpio/src/python/run_tests.in
(rev 0)
+++ gnuradio/branches/releases/3.1/gr-gpio/src/python/run_tests.in
2008-02-24 19:07:53 UTC (rev 7817)
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+# 1st parameter is absolute path to component source directory
+# 2nd parameter is absolute path to component build directory
+# 3rd parameter is path to Python QA directory
+
address@hidden@/run_tests.sh \
+ @abs_top_srcdir@/gr-gpio \
+ @abs_top_builddir@/gr-gpio \
+ @srcdir@
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- [Commit-gnuradio] r7817 - in gnuradio/branches/releases/3.1: . config gr-gpio gr-gpio/src gr-gpio/src/fpga gr-gpio/src/fpga/include gr-gpio/src/fpga/lib gr-gpio/src/fpga/top gr-gpio/src/lib gr-gpio/src/python,
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