[Commit-gnuradio] r7550 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx

[matt]

Author: matt
Date: 2008-02-03 21:21:24 -0700 (Sun, 03 Feb 2008)
New Revision: 7550

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
Log:
proper fifo space calculation


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-02-04 04:15:41 UTC 
(rev 7549)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-02-04 04:21:24 UTC 
(rev 7550)
@@ -64,7 +64,10 @@
      output reg    Rx_mac_pa,
      output reg    Rx_mac_sop,
      output        Rx_mac_err,
-     output        Rx_mac_eop );
+     output        Rx_mac_eop,
+     output [31:0] debug0,
+     output [31:0] debug1
+     );
    
   //-------------------------------------------------------------------------
   // Internal signals                                                          
    
@@ -303,8 +306,10 @@
 
    wire [RX_FF_DEPTH-1:0] fullness = Add_wr - Add_rd_ungray;
    always @(posedge Clk_MAC)
-     Fifo_space <= (1<<RX_FF_DEPTH) - {{(16-RX_FF_DEPTH){1'b0}},fullness};
-       
+     Fifo_space <= ((1<<RX_FF_DEPTH)-1) - {{(16-RX_FF_DEPTH){1'b0}},fullness};
+
+   assign                debug0 = 
{Almost_full,Full,Empty,Fifo_data_err,Fifo_data_drop, 
Add_wr_jump,Add_rd,Add_rd_ungray};
+   
   always @( posedge Clk_MAC or posedge Reset )
     if ( Reset )
       begin