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[Commit-gnuradio] r7549 - in usrp2/branches/developers/matt/newfifo/fpga
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From: |
matt |
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Subject: |
[Commit-gnuradio] r7549 - in usrp2/branches/developers/matt/newfifo/fpga: eth eth/rtl/verilog eth/rtl/verilog/MAC_rx top/u2_basic |
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Date: |
Sun, 3 Feb 2008 21:15:41 -0700 (MST) |
Author: matt
Date: 2008-02-03 21:15:41 -0700 (Sun, 03 Feb 2008)
New Revision: 7549
Modified:
usrp2/branches/developers/matt/newfifo/fpga/eth/mac_rxfifo_int.v
usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx.v
usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_top.v
usrp2/branches/developers/matt/newfifo/fpga/top/u2_basic/u2_basic.v
Log:
seems to be mostly working, with 2 extra lines
Modified: usrp2/branches/developers/matt/newfifo/fpga/eth/mac_rxfifo_int.v
===================================================================
--- usrp2/branches/developers/matt/newfifo/fpga/eth/mac_rxfifo_int.v
2008-02-04 03:54:52 UTC (rev 7548)
+++ usrp2/branches/developers/matt/newfifo/fpga/eth/mac_rxfifo_int.v
2008-02-04 04:15:41 UTC (rev 7549)
@@ -2,11 +2,10 @@
module mac_rxfifo_int
(input clk, input rst,
- input Rx_mac_ra,
+ input Rx_mac_empty,
output Rx_mac_rd,
input [31:0] Rx_mac_data,
input [1:0] Rx_mac_BE,
- input Rx_mac_pa,
input Rx_mac_sop,
input Rx_mac_eop,
input Rx_mac_err,
@@ -18,27 +17,54 @@
input wr_ready_i,
input wr_full_i);
- // From Claus --
- // The _BE fields are only valid when _eop is asserted.
- // 00 means all 4 bytes are valid, 01 means 1 byte (bit 31:24), 10 means 2
bytes, 11 means 3 bytes.
- // This goes for both Tx and Rx direction.
+ // Write side of short FIFO
+ // Inputs: full, Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err,
Rx_mac_data/BE
+ // Controls: write, datain, Rx_mac_rd
- // Outputs -- Rx_mac_rd, wr_write_o, wr_done_o, wr_error_o
+ wire write, full, read, empty, sop_o, eop_o, error_o;
- reg xfer_active;
+ // Write side of short FIFO
+ assign write = ~full & ~Rx_mac_empty;
+ assign Rx_mac_rd = write;
+
+ shortfifo #(.WIDTH(35)) mac_rx_sfifo
+ (.clk(clk),.rst(rst),.clear(0),
+
.datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full),
+ .dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty) );
+
+ // Read side of short FIFO
+ // Inputs: empty, dataout, wr_ready_i, wr_full_i
+ // Controls: read, wr_dat_o, wr_write_o, wr_done_o, wr_error_o
+
+ reg [1:0] rd_state;
+ localparam RD_IDLE = 0;
+ localparam RD_HAVEPKT = 1;
+ localparam RD_XFER = 2;
+ localparam RD_ERROR = 3;
+
always @(posedge clk)
if(rst)
- xfer_active <= 0;
- else if(wr_ready_i & Rx_mac_ra)
- xfer_active <= 1;
- else if(Rx_mac_eop | Rx_mac_err)
- xfer_active <= 0;
+ rd_state <= RD_IDLE;
+ else
+ case(rd_state)
+ RD_IDLE :
+ if(sop_o & ~empty)
+ rd_state <= RD_HAVEPKT;
+ RD_HAVEPKT :
+ if(wr_ready_i)
+ rd_state <= RD_XFER;
+ RD_XFER :
+ if(eop_o & ~empty)
+ rd_state <= RD_IDLE;
+ else if(wr_full_i)
+ rd_state <= RD_HAVEPKT;
+ RD_ERROR :
+ rd_state <= RD_IDLE;
+ endcase // case(rd_state)
- assign Rx_mac_rd = xfer_active;
-
- assign wr_write_o = Rx_mac_pa;
- assign wr_done_o = Rx_mac_eop;
- assign wr_error_o = Rx_mac_err;
- assign wr_dat_o = Rx_mac_data;
-
+ assign read = ~empty & ((rd_state == RD_XFER) |
((rd_state==RD_IDLE)&~sop_o));
+ assign wr_write_o = ~empty & (rd_state == RD_XFER);
+ assign wr_done_o = ~empty & (rd_state == RD_XFER) & eop_o;
+ assign wr_error_o = ~empty & (rd_state == RD_XFER) & error_o;
+
endmodule // mac_rxfifo_int
Modified:
usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
---
usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
2008-02-04 03:54:52 UTC (rev 7548)
+++
usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
2008-02-04 04:15:41 UTC (rev 7549)
@@ -47,9 +47,8 @@
input Fifo_data_en,
output Fifo_full,
input Fifo_data_err,
- input Fifo_data_drop,
input Fifo_data_end,
- output reg [15:0] Fifo_space,
+ output [15:0] Fifo_space,
// CPU
input RX_APPEND_CRC,
@@ -57,613 +56,119 @@
input [4:0] Rx_Lwmark,
// User interface
- output reg Rx_mac_ra,
+ output Rx_mac_empty,
input Rx_mac_rd,
output [31:0] Rx_mac_data,
output [1:0] Rx_mac_BE,
- output reg Rx_mac_pa,
- output reg Rx_mac_sop,
- output Rx_mac_err,
- output Rx_mac_eop );
-
- //-------------------------------------------------------------------------
- // Internal signals
- //-------------------------------------------------------------------------
+ output Rx_mac_sop,
+ output Rx_mac_eop,
+ output Rx_mac_err
+ );
- localparam State_byte3 = 4'h0;
- localparam State_byte2 = 4'h1;
- localparam State_byte1 = 4'h2;
- localparam State_byte0 = 4'h3;
- localparam State_be0 = 4'h4;
- localparam State_be3 = 4'h5;
- localparam State_be2 = 4'h6;
- localparam State_be1 = 4'h7;
- localparam State_err = 4'h8;
- localparam State_err_end = 4'h9;
- localparam State_idle = 4'ha;
-
- localparam SYS_read = 3'd0;
- localparam SYS_pause = 3'd1;
- localparam SYS_wait_end = 3'd2;
- localparam SYS_idle = 3'd3;
- localparam SYS_empty_err = 3'd4;
-
- reg [RX_FF_DEPTH-1:0] Add_wr;
- reg [RX_FF_DEPTH-1:0] Add_wr_ungray;
- reg [RX_FF_DEPTH-1:0] Add_wr_ungray_next;
- reg [RX_FF_DEPTH-1:0] Add_wr_gray;
- reg [RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
- reg [RX_FF_DEPTH-1:0] Add_wr_reg;
-
- reg [RX_FF_DEPTH-1:0] Add_rd;
- reg [RX_FF_DEPTH-1:0] Add_rd_gray;
- reg [RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
- reg [RX_FF_DEPTH-1:0] Add_rd_ungray;
- reg [RX_FF_DEPTH-1:0] Add_rd_ungray_next;
-
- reg [35:0] Din;
- reg [35:0] Din_tmp;
- reg [31:0] Din_tmp_reg;
- wire [35:0] Dout;
- reg Wr_en;
- reg Wr_en_tmp;
- reg Wr_en_ptr;
- wire [RX_FF_DEPTH-1:0] Add_wr_plus4;
- wire [RX_FF_DEPTH-1:0] Add_wr_plus3;
- wire [RX_FF_DEPTH-1:0] Add_wr_plus2;
- wire [RX_FF_DEPTH-1:0] Add_wr_plus1;
- reg Full;
- reg Almost_full;
-
- reg Empty;
- reg [3:0] Current_state;
- reg [2:0] Current_state_SYS;
- reg [5:0] Packet_number_inFF;
-
- reg [3:0] Next_state;
- reg [7:0] Fifo_data_byte1;
- reg [7:0] Fifo_data_byte2;
- reg [7:0] Fifo_data_byte3;
- reg Fifo_data_en_dl1;
- reg [7:0] Fifo_data_dl1;
- reg Rx_mac_sop_pre1, Rx_mac_sop_pre2;
-
- reg [2:0] Next_state_SYS;
- reg Packet_number_sub;
- wire Packet_number_add_edge;
- reg Packet_number_add_dl1;
- reg Packet_number_add_dl2;
- reg Packet_number_add;
- reg Packet_number_add_tmp;
- reg Packet_number_add_tmp_dl1;
- reg Packet_number_add_tmp_dl2;
-
- reg [35:0] Dout_dl1;
- reg [4:0] Fifo_data_count;
- reg Rx_mac_pa_pre;
- reg Add_wr_jump_tmp;
- reg Add_wr_jump_tmp_pl1;
- reg Add_wr_jump;
- reg Add_wr_jump_rd_pl1;
- reg [4:0] Rx_Hwmark_pl;
- reg [4:0] Rx_Lwmark_pl;
-
- //-------------------------------------------------------------------------
- // domain Clk_MAC,write data to dprom.a-port for write
- //-------------------------------------------------------------------------
-
- always @( posedge Clk_MAC or posedge Reset )
- if (Reset)
- Current_state <=State_idle;
- else
- Current_state <=Next_state;
-
- // Delay two clocks to match delay in Current_state FSM
- // NB: Fifo_data_error and Fifo_data_drop have same timing. The latter can
- // only be asserted when the former is also asserted
- reg [1:0] Fifo_data_drop_delayed;
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Fifo_data_drop_delayed <= 2'b00;
- else
- Fifo_data_drop_delayed <= { Fifo_data_drop_delayed[0], Fifo_data_drop };
-
- always @( Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end )
- case ( Current_state )
- State_idle:
- if ( Fifo_data_en )
- Next_state = State_byte3;
- else
- Next_state = Current_state;
-
- State_byte3:
- if ( Fifo_data_en )
- Next_state = State_byte2;
- else if ( Fifo_data_err )
- Next_state = State_err;
- else if ( Fifo_data_end )
- Next_state = State_be1;
- else
- Next_state = Current_state;
-
- State_byte2:
- if ( Fifo_data_en )
- Next_state = State_byte1;
- else if ( Fifo_data_err )
- Next_state = State_err;
- else if ( Fifo_data_end )
- Next_state = State_be2;
- else
- Next_state = Current_state;
-
- State_byte1:
- if ( Fifo_data_en )
- Next_state = State_byte0;
- else if ( Fifo_data_err )
- Next_state = State_err;
- else if (Fifo_data_end )
- Next_state = State_be3;
- else
- Next_state = Current_state;
-
- State_byte0:
- if ( Fifo_data_en )
- Next_state = State_byte3;
- else if ( Fifo_data_err )
- Next_state = State_err;
- else if ( Fifo_data_end )
- Next_state = State_be0;
- else
- Next_state = Current_state;
-
- State_be0,
- State_be1,
- State_be2,
- State_be3:
- Next_state = State_idle;
-
- State_err:
- Next_state = State_err_end;
-
- State_err_end:
- Next_state = State_idle;
-
- default:
- Next_state = State_idle;
- endcase
-
- // Save write pointer at the location where a new packet will start to allow
dropping
- // that packet entirely by reverting to this saved pointer!
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Add_wr_reg <=0;
- else if ( Current_state==State_idle )
- Add_wr_reg <= Add_wr;
-
- //
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Add_wr_gray <= 0;
- else
- begin : Add_wr_gray_loop
- integer i;
- Add_wr_gray[RX_FF_DEPTH-1] <= Add_wr[RX_FF_DEPTH-1];
- for ( i=RX_FF_DEPTH-2; i>=0; i=i-1 )
- Add_wr_gray[i] <= Add_wr[i+1] ^ Add_wr[i];
- end
-
- //
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Add_rd_gray_dl1 <= 0;
- else
- Add_rd_gray_dl1 <= Add_rd_gray;
-
- // CFH: Rewritten to not depend on simulation order - extremely dangerous
coding style!!!
- always @( * )
- begin : Add_rd_ungray_loop
- integer i;
- Add_rd_ungray_next[RX_FF_DEPTH-1] = Add_rd_gray_dl1[RX_FF_DEPTH-1];
- for ( i=RX_FF_DEPTH-2; i>=0; i=i-1 )
- Add_rd_ungray_next[i] = Add_rd_ungray_next[i+1] ^ Add_rd_gray_dl1[i];
- end
-
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Add_rd_ungray <= 0;
- else
- Add_rd_ungray <= Add_rd_ungray_next;
-
- assign Add_wr_plus1 = Add_wr + 1;
- assign Add_wr_plus2 = Add_wr + 2;
- assign Add_wr_plus3 = Add_wr + 3;
- assign Add_wr_plus4 = Add_wr + 4;
-
- always @ ( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Full <=0;
- else if ( Add_wr_plus1==Add_rd_ungray )
- Full <= 1;
- else
- Full <= 0;
-
- always @ ( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Almost_full <= 0;
- else if ( (Add_wr_plus4==Add_rd_ungray) ||
- (Add_wr_plus3==Add_rd_ungray) ||
- (Add_wr_plus2==Add_rd_ungray) ||
- (Add_wr_plus1==Add_rd_ungray)
- )
- Almost_full <= 1;
- else
- Almost_full <= 0;
-
- assign Fifo_full = Almost_full;
-
- wire [RX_FF_DEPTH-1:0] fullness = Add_wr - Add_rd_ungray;
- always @(posedge Clk_MAC)
- Fifo_space <= (1<<RX_FF_DEPTH) - {{(16-RX_FF_DEPTH){1'b0}},fullness};
-
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- begin
- Add_wr <= 0;
- Add_wr_jump <= 0;
- Add_wr_jump_tmp <= 0;
- Add_wr_jump_tmp_pl1 <= 0;
- end
- else
- begin
- Add_wr_jump_tmp_pl1 <= Add_wr_jump_tmp;
-
- if ( Fifo_data_drop_delayed[1] && (Current_state==State_err_end) )
- begin
- // Actually DROP the packet from the FIFO by reverting the FIFO
write pointer!!!
- Add_wr <= Add_wr_reg;
- Add_wr_jump <= 1;
- Add_wr_jump_tmp <= 1;
- end
- else
- begin
- if ( Wr_en && !Full )
- Add_wr <= Add_wr +1;
- if ( Add_wr_jump_tmp_pl1 )
- Add_wr_jump <=0 ;
-
- Add_wr_jump_tmp <= 0;
- end
- end
-
- //
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- begin
- Fifo_data_en_dl1 <= 0;
- Fifo_data_dl1 <= 0;
- Fifo_data_byte1 <= 0;
- Fifo_data_byte2 <= 0;
- Fifo_data_byte3 <= 0;
- end
- else
- begin
- Fifo_data_en_dl1 <= Fifo_data_en;
- Fifo_data_dl1 <= Fifo_data;
- if ( (Current_state==State_byte1) && Fifo_data_en_dl1 )
- Fifo_data_byte1 <= Fifo_data_dl1;
- if ( (Current_state==State_byte2) && Fifo_data_en_dl1 )
- Fifo_data_byte2 <= Fifo_data_dl1;
- if ( (Current_state==State_byte3) && Fifo_data_en_dl1 )
- Fifo_data_byte3 <= Fifo_data_dl1;
- end
-
- always @( * )
- case ( Current_state )
- State_be0:
- Din_tmp = {4'b1000, Fifo_data_byte3, Fifo_data_byte2, Fifo_data_byte1,
Fifo_data_dl1};
- State_be1:
- Din_tmp = {4'b1001, Fifo_data_byte3, 24'h0};
- State_be2:
- Din_tmp = {4'b1010, Fifo_data_byte3, Fifo_data_byte2, 16'h0};
- State_be3:
- Din_tmp = {4'b1011, Fifo_data_byte3, Fifo_data_byte2, Fifo_data_byte1,
8'h0};
- State_err:
- begin
-// $display( "%0t: Current_state=State_err, writing...", $time );
- Din_tmp = {4'b1101, 32'h0};
- end
- default:
- Din_tmp = {4'b0000, Fifo_data_byte3, Fifo_data_byte2, Fifo_data_byte1,
Fifo_data_dl1};
- endcase
-
- always @( * )
- if ( (Current_state==State_be0) || (Current_state==State_be1) ||
- (Current_state==State_be2) || (Current_state==State_be3) ||
- (Current_state==State_err) ||
- ( (Current_state==State_byte0) && Fifo_data_en ) )
- Wr_en_tmp = 1;
- else
- Wr_en_tmp = 0;
-
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Din_tmp_reg <= 0;
- else if( Wr_en_tmp )
- Din_tmp_reg <= Din_tmp[31:0];
-
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Wr_en_ptr <= 0;
- else if( Current_state==State_idle )
- Wr_en_ptr <= 0;
- else if( Wr_en_tmp )
- Wr_en_ptr <= 1;
-
- // If not append FCS, delay one cycle write data and Wr_en signal to drop FCS
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- begin
- Wr_en <= 0;
- Din <= 0;
- end
- else if( RX_APPEND_CRC )
- begin
- Wr_en <= Wr_en_tmp;
- Din <= Din_tmp;
- end
- else
- begin
- Wr_en <= Wr_en_tmp && Wr_en_ptr;
- Din <= {Din_tmp[35:32], Din_tmp_reg[31:0]};
- end
-
- // This signal for read side to handle the packet number in fifo
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Packet_number_add_tmp <= 0;
- else if ( (Current_state==State_be0) || (Current_state==State_be1) ||
- (Current_state==State_be2) || (Current_state==State_be3) ||
- (Current_state==State_err) )
- Packet_number_add_tmp <= 1;
- else
- Packet_number_add_tmp <= 0;
-
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- begin
- Packet_number_add_tmp_dl1 <= 0;
- Packet_number_add_tmp_dl2 <= 0;
- end
- else
- begin
- Packet_number_add_tmp_dl1 <= Packet_number_add_tmp;
- Packet_number_add_tmp_dl2 <= Packet_number_add_tmp_dl1;
- end
-
- // Packet_number_add delay to Din[35] is needed to make sure the data have
been written to ram.
- // expand to two cycles long almost=16 ns
- // If the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or
more clock cycles
- // CFH: TBD: piece of crap!!!!!!!
- always @( posedge Clk_MAC or posedge Reset )
- if ( Reset )
- Packet_number_add <= 0;
- else if ( Packet_number_add_tmp_dl1 || Packet_number_add_tmp_dl2 )
- Packet_number_add <= 1;
- else
- Packet_number_add <= 0;
-
- //-------------------------------------------------------------------------
- // Domain Clk_SYS,read data from dprom.b-port for read
- //-------------------------------------------------------------------------
+ reg [1:0] FF_state;
+ reg [2:0] PKT_state;
+ reg [31:0] staging;
+ reg [35:0] staging2;
+ reg line_ready, line_ready_d1;
+ wire sop_i, eop_i;
+ reg [1:0] be;
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Current_state_SYS <= SYS_idle;
+ always @(posedge Clk_MAC or posedge Reset)
+ if(Reset)
+ FF_state <= 0;
else
- Current_state_SYS <= Next_state_SYS;
+ if(Fifo_data_err | Fifo_data_end)
+ FF_state <= 0;
+ else if(Fifo_data_en)
+ FF_state <= FF_state + 1;
- always @*
- case ( Current_state_SYS )
- SYS_idle:
- if ( Rx_mac_rd && Rx_mac_ra && !Empty )
- Next_state_SYS = SYS_read;
- else if( Rx_mac_rd && Rx_mac_ra && Empty )
- Next_state_SYS = SYS_empty_err;
- else
- Next_state_SYS = Current_state_SYS;
-
- SYS_read:
- if ( !Rx_mac_rd )
- Next_state_SYS = SYS_pause;
- else if ( Dout[35] )
- Next_state_SYS = SYS_wait_end;
- else if ( Empty )
- Next_state_SYS = SYS_empty_err;
- else
- Next_state_SYS = Current_state_SYS;
-
- SYS_pause:
- if ( Rx_mac_rd )
- Next_state_SYS = SYS_read;
- else
- Next_state_SYS = Current_state_SYS;
-
- SYS_empty_err:
- if ( !Empty )
- Next_state_SYS = SYS_read;
- else
- Next_state_SYS = Current_state_SYS;
-
- SYS_wait_end:
- if ( !Rx_mac_rd )
- Next_state_SYS = SYS_idle;
- else
- Next_state_SYS = Current_state_SYS;
-
- default:
- Next_state_SYS = SYS_idle;
- endcase
-
- // Gen Rx_mac_ra
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- begin
- Packet_number_add_dl1 <= 0;
- Packet_number_add_dl2 <= 0;
- end
- else
- begin
- Packet_number_add_dl1 <= Packet_number_add;
- Packet_number_add_dl2 <= Packet_number_add_dl1;
- end
-
- assign Packet_number_add_edge = Packet_number_add_dl1 &
!Packet_number_add_dl2;
-
- always @( Current_state_SYS or Next_state_SYS )
- if ( (Current_state_SYS==SYS_read) && (Next_state_SYS==SYS_wait_end) )
- Packet_number_sub = 1;
+ always @(posedge Clk_MAC or posedge Reset)
+ if(Reset)
+ staging[31:0] <= 0;
+ else if(Fifo_data_en)
+ case(FF_state)
+ 0 : staging[31:24] <= Fifo_data;
+ 1 : staging[23:16] <= Fifo_data;
+ 2 : staging[15:8] <= Fifo_data;
+ 3 : staging[7:0] <= Fifo_data;
+ endcase // case(FF_state)
+
+ localparam PKT_idle = 0;
+ localparam PKT_sop = 1;
+ localparam PKT_pkt = 2;
+ localparam PKT_end = 3;
+ localparam PKT_err = 4;
+
+ always @(posedge Clk_MAC or posedge Reset)
+ if(Reset)
+ PKT_state <= 0;
else
- Packet_number_sub = 0;
+ case(PKT_state)
+ PKT_idle :
+ if(Fifo_data_en)
+ PKT_state <= PKT_sop;
+ PKT_sop, PKT_pkt :
+ if(Fifo_data_err | (line_ready & Fifo_full))
+ PKT_state <= PKT_err;
+ else if(Fifo_data_end)
+ PKT_state <= PKT_end;
+ else if(line_ready & ~Fifo_full)
+ PKT_state <= PKT_pkt;
+ PKT_end :
+ PKT_state <= PKT_idle;
+ PKT_err :
+ if(~Fifo_full)
+ PKT_state <= PKT_idle;
+ endcase // case(PKT_state)
+
+ assign sop_i = (PKT_state == PKT_sop);
+ assign eop_i = (PKT_state == PKT_end);
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Packet_number_inFF <= 0;
- else if ( Packet_number_add_edge && !Packet_number_sub )
- Packet_number_inFF <= Packet_number_inFF + 1;
- else if ( !Packet_number_add_edge && Packet_number_sub &&
(Packet_number_inFF!=0) )
- Packet_number_inFF <= Packet_number_inFF - 1;
+ always @(posedge Clk_MAC)
+ if(line_ready)
+ staging2 <= {sop_i, eop_i, be[1:0], staging};
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Fifo_data_count <= 0;
+ always @(posedge Clk_MAC)
+ if(Reset)
+ line_ready <= 0;
+ else if((Fifo_data_en & (FF_state==2'd3)) | Fifo_data_end | Fifo_data_err)
+ line_ready <= 1;
else
- Fifo_data_count <=
- Add_wr_ungray[RX_FF_DEPTH-1:RX_FF_DEPTH-5] -
- Add_rd[RX_FF_DEPTH-1:RX_FF_DEPTH-5];
+ line_ready <= 0;
+
+ always @(posedge Clk_MAC)
+ line_ready_d1 <= line_ready;
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- begin
- Rx_Hwmark_pl <=0;
- Rx_Lwmark_pl <=0;
- end
+ always @(posedge Clk_MAC)
+ if(Fifo_data_end | Fifo_data_err)
+ be <= FF_state;
else
- begin
- Rx_Hwmark_pl <= Rx_Hwmark;
- Rx_Lwmark_pl <= Rx_Lwmark;
- end
+ be <= 0;
- // Control Add_rd signal
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Add_rd <= 0;
- else if ( (Current_state_SYS==SYS_read) && !Dout[35] )
- Add_rd <= Add_rd + 1;
-
- //
- always @( posedge Reset or posedge Clk_SYS )
- if ( Reset )
- Add_rd_gray <= 0;
- else
- begin : Add_rd_gray_loop
- integer i;
- Add_rd_gray[RX_FF_DEPTH-1] <= Add_rd[RX_FF_DEPTH-1];
- for ( i=RX_FF_DEPTH-2; i>=0; i=i-1 )
- Add_rd_gray[i] <= Add_rd[i+1] ^ Add_rd[i];
- end
-
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- begin
- Add_wr_gray_dl1 <= 0;
- Add_wr_jump_rd_pl1 <= 0;
- end
- else
- begin
- Add_wr_gray_dl1 <= Add_wr_gray;
- Add_wr_jump_rd_pl1 <= Add_wr_jump;
- end
-
- // CFH: Rewritten to not depend on simulation order - extremely dangerous
coding style!!!
- always @( * )
- begin : Add_wr_ungray_loop
- integer i;
- Add_wr_ungray_next[RX_FF_DEPTH-1] = Add_wr_gray_dl1[RX_FF_DEPTH-1];
- for ( i=RX_FF_DEPTH-2; i>=0; i=i-1 )
- Add_wr_ungray_next[i] = Add_wr_ungray_next[i+1] ^ Add_wr_gray_dl1[i];
- end
-
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Add_wr_ungray <= 0;
- else if ( !Add_wr_jump_rd_pl1 )
- Add_wr_ungray <= Add_wr_ungray_next;
-
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Empty <=1;
- else if ( Add_rd==Add_wr_ungray )
- Empty <= 1;
- else
- Empty <= 0;
-
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Dout_dl1 <= 0;
- else
- Dout_dl1 <= Dout;
-
- assign Rx_mac_data = Dout_dl1[31:0]; // No need for --> |
{32{Rx_mac_err}};
- assign Rx_mac_BE = Dout_dl1[33:32];
- assign Rx_mac_err = Dout_dl1[34];
- assign Rx_mac_eop = Dout_dl1[35];
-
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Rx_mac_ra <= 0;
- else if ( (Packet_number_inFF==0) && (Fifo_data_count <= Rx_Lwmark_pl) )
- Rx_mac_ra <=0;
- else if ( (Packet_number_inFF >= 1) || (Fifo_data_count >= Rx_Hwmark_pl) )
- Rx_mac_ra <= 1;
-
- // Aligned to Addr_rd
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Rx_mac_pa_pre <= 0;
- else if ( (Current_state_SYS==SYS_read) && !Dout[35] )
- Rx_mac_pa_pre <= 1;
- else
- Rx_mac_pa_pre <= 0;
-
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Rx_mac_pa <= 0;
- else
- Rx_mac_pa <= Rx_mac_pa_pre;
-
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- Rx_mac_sop_pre2 <= 0;
- else if ( (Current_state_SYS==SYS_idle) && (Next_state_SYS==SYS_read) )
- Rx_mac_sop_pre2 <= 1;
- else
- Rx_mac_sop_pre2 <= 0;
+ wire sop_o, eop_o, empty;
+ wire [1:0] be_o;
+ wire [RX_FF_DEPTH-1:0] occupied;
+ wire [31:0] dataout;
+ fifo_2clock #(.DWIDTH(36),.AWIDTH(RX_FF_DEPTH)) mac_rx_fifo
+ (.wclk(Clk_MAC),.datain((PKT_state==PKT_err) ? 36'hF_FFFF_FFFF :
staging2),.write(~Fifo_full & (line_ready_d1|(PKT_state==PKT_err))),
+ .full(Fifo_full),.level_wclk(occupied),
+
.rclk(Clk_SYS),.dataout({sop_o,eop_o,be_o[1:0],dataout}),.read(Rx_mac_rd),
+ .empty(empty),.level_rclk(),
+ .arst(Reset) );
+ assign Fifo_space[15:RX_FF_DEPTH] = 0;
+ assign Fifo_space[RX_FF_DEPTH-1:0] = ~occupied;
- always @( posedge Clk_SYS or posedge Reset )
- if ( Reset )
- begin
- Rx_mac_sop_pre1 <= 0;
- Rx_mac_sop <= 0;
- end
- else
- begin
- Rx_mac_sop_pre1 <= Rx_mac_sop_pre2;
- Rx_mac_sop <= Rx_mac_sop_pre1;
- end
+ // mac side fifo interface
+ // Input - Rx_mac_rd
+ // Output - Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err,
Rx_mac_data, Rx_mac_BE
+
+ assign Rx_mac_BE = be_o;
+ assign Rx_mac_sop = sop_o & ~eop_o;
+ assign Rx_mac_eop = eop_o;
+ assign Rx_mac_err = sop_o & eop_o;
+ assign Rx_mac_empty = empty;
+ assign Rx_mac_data = dataout;
- // Instantiation of dual-ported RAM
- ram_2port #(.DWIDTH(36),.AWIDTH(RX_FF_DEPTH)) mac_rx_ff_ram
- (.clka(Clk_MAC),.ena(1'b1),.wea(Wr_en),.addra(Add_wr),.dia(Din),.doa(),
-
.clkb(Clk_SYS),.enb(1'b1),.web(1'b0),.addrb(Add_rd),.dib(36'b0),.dob(Dout) );
-
endmodule // MAC_rx_FF
+
+// FIXME Should we send out an "almost full" signal instead of full?
Modified: usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx.v
===================================================================
--- usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx.v
2008-02-04 03:54:52 UTC (rev 7548)
+++ usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx.v
2008-02-04 04:15:41 UTC (rev 7549)
@@ -68,14 +68,13 @@
output pause_quanta_val,
output [15:0] rx_fifo_space,
//user interface
-output Rx_mac_ra ,
+output Rx_mac_empty,
input Rx_mac_rd ,
output [31:0] Rx_mac_data ,
output [1:0] Rx_mac_BE ,
-output Rx_mac_pa ,
output Rx_mac_sop ,
+output Rx_mac_eop ,
output Rx_mac_err ,
-output Rx_mac_eop ,
//CPU
input MAC_rx_add_chk_en ,
input [7:0] MAC_add_prom_data ,
@@ -95,7 +94,8 @@
output [15:0] Rx_pkt_length_rmon ,
output Rx_apply_rmon ,
output [2:0] Rx_pkt_err_type_rmon ,
-output [2:0] Rx_pkt_type_rmon
+output [2:0] Rx_pkt_type_rmon ,
+ output [31:0] debug
);
//******************************************************************************
//internal signals
@@ -166,6 +166,8 @@
.RX_MIN_LENGTH (RX_MIN_LENGTH )
);
+ assign debug = {'d0, Fifo_data_en, Fifo_data_err,
Fifo_data_end,Fifo_full};
+
MAC_rx_FF #(.RX_FF_DEPTH(RX_FF_DEPTH)) U_MAC_rx_FF (
.Reset (Reset ),
.Clk_MAC (Clk ),
@@ -175,7 +177,7 @@
.Fifo_data_en (Fifo_data_en ),
.Fifo_full (Fifo_full ),
.Fifo_data_err (Fifo_data_err ),
-.Fifo_data_drop (Fifo_data_drop ),
+//.Fifo_data_drop (Fifo_data_drop ),
.Fifo_data_end (Fifo_data_end ),
.Fifo_space (rx_fifo_space ),
//CPU (//CPU ),
@@ -183,14 +185,13 @@
.Rx_Lwmark (Rx_Lwmark ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
//user interface (//user interface ),
-.Rx_mac_ra (Rx_mac_ra ),
+.Rx_mac_empty (Rx_mac_empty ),
.Rx_mac_rd (Rx_mac_rd ),
.Rx_mac_data (Rx_mac_data ),
.Rx_mac_BE (Rx_mac_BE ),
.Rx_mac_sop (Rx_mac_sop ),
-.Rx_mac_pa (Rx_mac_pa ),
-.Rx_mac_err (Rx_mac_err ),
-.Rx_mac_eop (Rx_mac_eop )
+.Rx_mac_eop (Rx_mac_eop ),
+.Rx_mac_err (Rx_mac_err )
);
Broadcast_filter U_Broadcast_filter
Modified: usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_top.v
2008-02-04 03:54:52 UTC (rev 7548)
+++ usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_top.v
2008-02-04 04:15:41 UTC (rev 7549)
@@ -71,14 +71,13 @@
output ACK_O, // Acknowledge output � single high pulse
// User (packet) interface
- output Rx_mac_ra,
+ output Rx_mac_empty,
input Rx_mac_rd,
output [31:0] Rx_mac_data,
output [1:0] Rx_mac_BE,
- output Rx_mac_pa,
output Rx_mac_sop,
+ output Rx_mac_eop,
output Rx_mac_err,
- output Rx_mac_eop,
output Tx_mac_wa,
input Tx_mac_wr,
@@ -109,6 +108,8 @@
output [31:0] debug1
);
+ wire [31:0] debug_rx;
+
//-------------------------------------------------------------------------
// Local declarations
//-------------------------------------------------------------------------
@@ -227,14 +228,13 @@
.rx_fifo_space ( rx_fifo_space ),
// User interface
- .Rx_mac_ra ( Rx_mac_ra ),
+ .Rx_mac_empty ( Rx_mac_empty ),
.Rx_mac_rd ( Rx_mac_rd ),
.Rx_mac_data ( Rx_mac_data ),
.Rx_mac_BE ( Rx_mac_BE ),
- .Rx_mac_pa ( Rx_mac_pa ),
.Rx_mac_sop ( Rx_mac_sop ),
+ .Rx_mac_eop ( Rx_mac_eop ),
.Rx_mac_err ( Rx_mac_err ),
- .Rx_mac_eop ( Rx_mac_eop ),
// CPU
.MAC_rx_add_chk_en ( MAC_rx_add_chk_en ),
@@ -256,7 +256,8 @@
.Rx_pkt_length_rmon ( Rx_pkt_length_rmon ),
.Rx_apply_rmon ( Rx_apply_rmon ),
.Rx_pkt_err_type_rmon ( Rx_pkt_err_type_rmon ),
- .Rx_pkt_type_rmon ( Rx_pkt_type_rmon )
+ .Rx_pkt_type_rmon ( Rx_pkt_type_rmon ),
+ .debug(debug_rx)
);
MAC_tx #(.TX_FF_DEPTH(TX_FF_DEPTH))
@@ -504,8 +505,8 @@
.UpdateMIIRX_DATAReg ( UpdateMIIRX_DATAReg )
);
- assign debug0 = {{tx_pause_en,pause_apply, pause_quanta_sub,
pause_quanta_val, xon_gen, xon_gen_complete, xoff_gen, xoff_gen_complete},
-
{Rx_mac_err,Rx_mac_ra,Rx_mac_rd,Rx_mac_pa,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},
+ assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen,
xoff_gen_complete},
+
{1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},
{rx_fifo_space}};
assign debug1 = 32'd0;
endmodule
Modified: usrp2/branches/developers/matt/newfifo/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/branches/developers/matt/newfifo/fpga/top/u2_basic/u2_basic.v
2008-02-04 03:54:52 UTC (rev 7548)
+++ usrp2/branches/developers/matt/newfifo/fpga/top/u2_basic/u2_basic.v
2008-02-04 04:15:41 UTC (rev 7549)
@@ -402,7 +402,7 @@
// Ethernet MAC Slave #6
wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
- wire Rx_mac_ra, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_pa,
Rx_mac_err;
+ wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err;
wire [31:0] Tx_mac_data, Rx_mac_data;
wire [1:0] Tx_mac_BE, Rx_mac_BE;
@@ -411,8 +411,8 @@
(.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),.Speed(),
.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
.WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack),
-
.Rx_mac_ra(Rx_mac_ra),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE),
-
.Rx_mac_pa(Rx_mac_pa),.Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
+
.Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE),
+ .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
.Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
.Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
.Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),
@@ -426,8 +426,8 @@
mac_rxfifo_int mac_rxfifo_int
(.clk(dsp_clk),.rst(dsp_rst),
- .Rx_mac_ra(Rx_mac_ra),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
- .Rx_mac_BE(Rx_mac_BE),.Rx_mac_pa(Rx_mac_pa),.Rx_mac_sop(Rx_mac_sop),
+
.Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
+ .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop),
.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
.wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
.wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full) );
@@ -609,9 +609,10 @@
assign debug_clk[0] = wb_clk;
assign debug_clk[1] = dsp_clk;
assign debug_gpio_0 = 32'd0; // Not used b/c of ATR
- assign debug_gpio_1 =
{{uart_tx_o,proc_int,overrun,underrun,timer_int,buffer_int,2'b0},
- GMII_TXD,
- GMII_RXD,
-
{GMII_TX_EN,GMII_RX_DV,Rx_mac_ra,Rx_mac_pa,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop}
};
+ assign debug_gpio_1 =
{{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
+ //GMII_TXD,
+ //GMII_RXD,
+ {2'b0,iwb_adr[13:0]},
+
{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full}
};
endmodule // u2_basic
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- [Commit-gnuradio] r7549 - in usrp2/branches/developers/matt/newfifo/fpga: eth eth/rtl/verilog eth/rtl/verilog/MAC_rx top/u2_basic,
matt <=