[Commit-gnuradio] r7543 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-02-02 01:34:40 -0700 (Sat, 02 Feb 2008)
New Revision: 7543

Modified:
   usrp2/trunk/fpga/control_lib/fifo_2clock.v
Log:
register the level signals


Modified: usrp2/trunk/fpga/control_lib/fifo_2clock.v
===================================================================
--- usrp2/trunk/fpga/control_lib/fifo_2clock.v  2008-02-02 08:33:50 UTC (rev 
7542)
+++ usrp2/trunk/fpga/control_lib/fifo_2clock.v  2008-02-02 08:34:40 UTC (rev 
7543)
@@ -1,8 +1,8 @@
 
 module fifo_2clock
   #(parameter DWIDTH=32, AWIDTH=9)
-    (input wclk, input [DWIDTH-1:0] datain, input write, output full, output 
[AWIDTH-1:0] level_wclk,
-     input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output 
[AWIDTH-1:0] level_rclk,
+    (input wclk, input [DWIDTH-1:0] datain, input write, output full, output 
reg [AWIDTH-1:0] level_wclk,
+     input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output 
reg [AWIDTH-1:0] level_rclk,
      input arst);
 
    reg [AWIDTH-1:0] wr_addr, rd_addr;
@@ -55,10 +55,12 @@
      (.clk_in(rclk),.addr_in(rd_addr),
       .clk_out(wclk),.addr_out(rd_addr_wclk) );
 
-   // Generate fullness info, these are approximate 
+   // Generate fullness info, these are approximate and may be delayed 
    // and are only for higher-level flow control.  
    // Only full and empty are guaranteed exact.
-   assign          level_wclk = wr_addr - rd_addr_wclk;
-   assign          level_rclk = wr_addr_rclk - rd_addr;
+   always @(posedge wclk) 
+     level_wclk <= wr_addr - rd_addr_wclk;
+   always @(posedge rclk) 
+     level_rclk <= wr_addr_rclk - rd_addr;
    
 endmodule // fifo_2clock