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[Commit-gnuradio] r6723 - gnuradio/branches/developers/matt/u2f/opencore
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From: |
matt |
|
Subject: |
[Commit-gnuradio] r6723 - gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog |
|
Date: |
Sun, 28 Oct 2007 16:32:17 -0600 (MDT) |
Author: matt
Date: 2007-10-28 16:32:17 -0600 (Sun, 28 Oct 2007)
New Revision: 6723
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
Log:
update from Shawn Tan, hopefully fixes the problem where an interrupt would
never happen if there was never a fully atomic pipeline of instructions (i.e.
in an infinite loop).
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-10-28 22:19:09 UTC (rev 6722)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-10-28 22:32:17 UTC (rev 6723)
@@ -86,7 +86,7 @@
input [15:0] rIMM;
input [4:0] rRD, rRA;
input [1:0] rMXLDST;
- input [1:0] rFSM;
+ input [2:0] rFSM;
input nclk, prst, drun, prun;
@@ -179,6 +179,7 @@
Performs shift instructions as well as sign extension. This is
done in parallel with the other operations.
*/
+
wire wSRAC, wSRCC, wSRLC, wRES_SC;
wire [31:0] wSRA,wSRC, wSRL, wSEXT8, wSEXT16, wRES_S;
assign {wSRAC,wSRA} = {wOPA[0],wOPA[0],wOPA[31:1]};
@@ -251,10 +252,10 @@
reg rMSR_IE, xMSR_IE;
wire fMTS = (rOPC == 6'o45) & rIMM[14];
- always @(/*AUTOSENSE*/fMTS or rMSR_C or rMXALU or rOPC or rRES_AC
- or rRES_SC or wOPA)
+ always @(/*AUTOSENSE*/drun or fMTS or rMSR_C or rMXALU or rOPC
+ or rRES_AC or rRES_SC or wOPA)
case (rMXALU)
- 2'o0: xMSR_C <= #1 (rOPC[2]) ? rMSR_C : rRES_AC;
+ 2'o0: xMSR_C <= #1 !(rOPC[5] | rOPC[2] | !drun) ? rRES_AC : rMSR_C;
2'o2: xMSR_C <= #1 rRES_SC;
2'o1: xMSR_C <= #1 (fMTS) ? wOPA[2] : rMSR_C;
default: xMSR_C <= #1 rMSR_C;
@@ -262,7 +263,7 @@
wire fRTID = (rOPC == 6'o55) & rRD[0];
always @(/*AUTOSENSE*/fMTS or fRTID or rFSM or rMSR_IE or wOPA) begin
- xMSR_IE <= (rFSM == 2'o1) ? 1'b0 :
+ xMSR_IE <= (rFSM == 3'o4) ? 1'b0 :
(fRTID) ? 1'b1 :
(fMTS) ? wOPA[1] :
rMSR_IE;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
2007-10-28 22:19:09 UTC (rev 6722)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
2007-10-28 22:32:17 UTC (rev 6723)
@@ -53,13 +53,12 @@
// Outputs
rFSM, nclk, prst, prun, frun, drun,
// Inputs
- sys_rst_i, sys_clk_i, sys_int_i, sys_exc_i, rIWBSTB, iwb_ack_i,
- rDWBSTB, dwb_ack_i, rBRA, rDLY, iwb_dat_i, rMSR_IE
+ sys_rst_i, sys_clk_i, sys_int_i, rIWBSTB, iwb_ack_i, rDWBSTB,
+ dwb_ack_i, rBRA, rDLY, rMSR_IE, rATOM
);
// System
input sys_rst_i, sys_clk_i;
input sys_int_i;
- input sys_exc_i;
// Instruction WB
input rIWBSTB;
@@ -71,11 +70,10 @@
// Internal
input rBRA, rDLY;
- input [31:0] iwb_dat_i;
input rMSR_IE;
+ input [1:0] rATOM;
- output [1:0] rFSM;
- //, rLDST;
+ output [2:0] rFSM;
output nclk, prst, prun;
output frun, drun;
@@ -96,7 +94,9 @@
TODO: Exceptions
*/
- wire fINT;
+
+ wire wINT = sys_int_i & rMSR_IE;
+ wire fATOM = (rATOM == 2'o3) | (rATOM == 2'o1);
reg [2:0] rEXC, rINT;
always @(negedge nclk)
if (prst) begin
@@ -105,8 +105,7 @@
rINT <= 3'h0;
// End of automatics
end else if (prun) begin
- //rEXC <= #1 {rEXC[1:0], sys_exc_i};
- rINT <= #1 {rINT[1:0], sys_int_i};
+ rINT <= #1 {rINT[1:0], wINT};
end
/**
@@ -118,71 +117,35 @@
TODO: Implement Exceptions
*/
- parameter [1:0]
- FSM_RUN = 2'o0,
- FSM_SWEXC = 2'o3,
- FSM_HWEXC = 2'o2,
- FSM_HWINT = 2'o1;
- reg [1:0] rFSM, rNXT;
+ parameter [2:0]
+ FSM_RUN = 3'o0,
+ FSM_DEB = 3'o1,
+ FSM_ATM = 3'o2,
+ FSM_CHK = 3'o3,
+ FSM_INT = 3'o4;
+
+ reg [2:0] rFSM, rNXT;
+
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
- rFSM <= 2'h0;
+ rFSM <= 3'h0;
// End of automatics
end else if (prun) begin
rFSM <= #1 rNXT;
end
- always @(/*AUTOSENSE*/fINT or rFSM)
+ always @(/*AUTOSENSE*/fATOM or rFSM or wINT)
case (rFSM)
- FSM_HWEXC: rNXT <= FSM_RUN;
- //FSM_SWEXC: rNXT <= FSM_RUN;
- FSM_HWINT: rNXT <= FSM_RUN;
- default: begin
- rNXT <= //(rEXC == 3'h3) ? FSM_HWEXC :
- (fINT) ? FSM_HWINT :
- FSM_RUN;
- end
+ // Edge detection
+ FSM_RUN: rNXT <= (wINT) ? FSM_DEB : FSM_RUN;
+ FSM_DEB: rNXT <= (wINT) ? FSM_ATM : FSM_RUN;
+ FSM_ATM: rNXT <= (fATOM) ? FSM_INT : FSM_ATM;
+ FSM_INT: rNXT <= FSM_RUN;
+ default: rNXT <= FSM_RUN;
endcase // case (rFSM)
-
- /**
- Interrupt Check
- ---------------
- It checks to make sure that all the instructions in the pipeline
- are atomic before allowing the detection of interrupts. Empirical
- response latency is 3-7 cycles.
- */
-
- wire [5:0] rOPC = iwb_dat_i[31:26];
- reg [2:0] rHWINT;
- reg [1:0] rNCLR;
- wire fCLR = ~|rNCLR;
- wire fNCLR = ({rOPC[5:4],rOPC[2:1]} == 4'b1011) | (rOPC == 6'o54) |
(rOPC == 6'o55);
- assign fINT = (rHWINT == 3'o3) & fCLR;
-
- always @(negedge nclk)
- if (prst) begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- rHWINT <= 3'h0;
- // End of automatics
- end else if (fINT) begin
- rHWINT <= 3'o0;
- end else if (prun & fCLR & rMSR_IE) begin
- rHWINT <= {rHWINT[1:0],sys_int_i};
- end
-
- always @(negedge nclk)
- if (prst) begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- rNCLR <= 2'h0;
- // End of automatics
- end else if (prun) begin
- rNCLR <= {rNCLR[0], fNCLR};
- end
/**
Bubble
@@ -191,8 +154,8 @@
*/
reg [1:0] rRUN, xRUN;
- wire fXCE = ~|rFSM;
- assign {drun,frun} = {xRUN[1] & fXCE , xRUN[0] & fXCE};
+ wire fXCE = ~rFSM[2];
+ assign {drun,frun} = {xRUN[1] & fXCE , xRUN[0] & fXCE & !(fATOM &
(rFSM==FSM_ATM))};
always @(/*AUTOSENSE*/rBRA or rDLY) begin
xRUN <= {~(rBRA ^ rDLY), ~rBRA};
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-10-28 22:19:09 UTC (rev 6722)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-10-28 22:32:17 UTC (rev 6723)
@@ -56,8 +56,8 @@
iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
dwb_adr_o,
// Inputs
- sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i, iwb_ack_i,
- dwb_dat_i, dwb_ack_i
+ sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
+ dwb_ack_i
);
// Instruction WB address space
parameter ISIZ = 32;
@@ -81,7 +81,6 @@
input iwb_ack_i; // To control of aeMB_control.v
input [31:0] iwb_dat_i; // To fetch of
aeMB_fetch.v, ...
input sys_clk_i; // To control of aeMB_control.v
- input sys_exc_i; // To control of aeMB_control.v
input sys_int_i; // To control of aeMB_control.v
input sys_rst_i; // To control of aeMB_control.v
// End of automatics
@@ -92,12 +91,13 @@
wire nclk; // From control of
aeMB_control.v
wire prst; // From control of
aeMB_control.v
wire prun; // From control of
aeMB_control.v
+ wire [1:0] rATOM; // From decode of aeMB_decode.v
wire rBRA; // From decode of
aeMB_decode.v
wire rDLY; // From decode of
aeMB_decode.v
wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v
wire rDWBSTB; // From decode of
aeMB_decode.v
wire rDWBWE; // From decode of
aeMB_decode.v
- wire [1:0] rFSM; // From control of
aeMB_control.v
+ wire [2:0] rFSM; // From control of
aeMB_control.v
wire [15:0] rIMM; // From decode of aeMB_decode.v
wire rIWBSTB; // From fetch of
aeMB_fetch.v
wire rLNK; // From decode of
aeMB_decode.v
@@ -136,7 +136,7 @@
.rRB (rRB[4:0]),
.rRD (rRD[4:0]),
.rRESULT (rRESULT[31:0]),
- .rFSM (rFSM[1:0]),
+ .rFSM (rFSM[2:0]),
.rPC (rPC[31:0]),
.rOPC (rOPC[5:0]),
.rDWBSEL (rDWBSEL[3:0]),
@@ -159,14 +159,14 @@
.nclk (nclk),
.prst (prst),
.prun (prun),
- .rFSM (rFSM[1:0]),
+ .rFSM (rFSM[2:0]),
.rBRA (rBRA),
.rRESULT (rRESULT[31:0]));
aeMB_control
control (/*AUTOINST*/
// Outputs
- .rFSM (rFSM[1:0]),
+ .rFSM (rFSM[2:0]),
.nclk (nclk),
.prst (prst),
.prun (prun),
@@ -176,15 +176,14 @@
.sys_rst_i (sys_rst_i),
.sys_clk_i (sys_clk_i),
.sys_int_i (sys_int_i),
- .sys_exc_i (sys_exc_i),
.rIWBSTB (rIWBSTB),
.iwb_ack_i (iwb_ack_i),
.rDWBSTB (rDWBSTB),
.dwb_ack_i (dwb_ack_i),
.rBRA (rBRA),
.rDLY (rDLY),
- .iwb_dat_i (iwb_dat_i[31:0]),
- .rMSR_IE (rMSR_IE));
+ .rMSR_IE (rMSR_IE),
+ .rATOM (rATOM[1:0]));
aeMB_aslu #(DSIZ)
aslu (/*AUTOINST*/
@@ -210,7 +209,7 @@
.rRD (rRD[4:0]),
.rRA (rRA[4:0]),
.rMXLDST (rMXLDST[1:0]),
- .rFSM (rFSM[1:0]),
+ .rFSM (rFSM[2:0]),
.nclk (nclk),
.prst (prst),
.drun (drun),
@@ -235,6 +234,7 @@
.rBRA (rBRA),
.rRWE (rRWE),
.rMXLDST (rMXLDST[1:0]),
+ .rATOM (rATOM[1:0]),
.dwb_stb_o (dwb_stb_o),
.dwb_we_o (dwb_we_o),
// Inputs
@@ -242,7 +242,7 @@
.rDWBSEL (rDWBSEL[3:0]),
.rREGA (rREGA[31:0]),
.rRESULT (rRESULT[31:0]),
- .rFSM (rFSM[1:0]),
+ .rFSM (rFSM[2:0]),
.iwb_dat_i (iwb_dat_i[31:0]),
.nclk (nclk),
.prst (prst),
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
2007-10-28 22:19:09 UTC (rev 6722)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
2007-10-28 22:32:17 UTC (rev 6723)
@@ -46,28 +46,7 @@
.dwb_dat_i(dwb_dat_i),
.dwb_dat_o(dwb_dat_o),
- .sys_int_i(sys_int_i),
- .sys_exc_i(sys_exc_i) );
+ .sys_int_i(sys_int_i) );
+ //.sys_exc_i(sys_exc_i) );
endmodule // aeMB_core_BE
-
-// No longer needed byte-mangling
-/*
- .iwb_dat_i({iwb_dat_i[7:0],
- iwb_dat_i[15:8],
- iwb_dat_i[23:16],
- iwb_dat_i[31:24]}),
-
- .dwb_sel_o({dwb_sel_o[0],
- dwb_sel_o[1],
- dwb_sel_o[2],
- dwb_sel_o[3]}),
- .dwb_dat_i({dwb_dat_i[7:0],
- dwb_dat_i[15:8],
- dwb_dat_i[23:16],
- dwb_dat_i[31:24]}),
- .dwb_dat_o({dwb_dat_o[7:0],
- dwb_dat_o[15:8],
- dwb_dat_o[23:16],
- dwb_dat_o[31:24]}),
-*/
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-10-28 22:19:09 UTC (rev 6722)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-10-28 22:32:17 UTC (rev 6723)
@@ -61,7 +61,8 @@
module aeMB_decode (/*AUTOARG*/
// Outputs
rSIMM, rMXALU, rMXSRC, rMXTGT, rRA, rRB, rRD, rOPC, rIMM, rDWBSTB,
- rDWBWE, rDLY, rLNK, rBRA, rRWE, rMXLDST, dwb_stb_o, dwb_we_o,
+ rDWBWE, rDLY, rLNK, rBRA, rRWE, rMXLDST, rATOM, dwb_stb_o,
+ dwb_we_o,
// Inputs
sDWBDAT, rDWBSEL, rREGA, rRESULT, rFSM, iwb_dat_i, nclk, prst,
drun, frun, prun
@@ -76,10 +77,12 @@
output rDWBSTB, rDWBWE;
output rDLY, rLNK, rBRA, rRWE;
output [1:0] rMXLDST;
+ output [1:0] rATOM;
+
input [31:0] sDWBDAT;
input [3:0] rDWBSEL;
input [31:0] rREGA, rRESULT;
- input [1:0] rFSM;
+ input [2:0] rFSM;
// External I/F
input [31:0] iwb_dat_i;
@@ -122,7 +125,7 @@
assign rIMM = wIMM;
*/
- always @(/*AUTOSENSE*/frun or wIMM or wOPC or wRA or wRB or wRD)
+ always @(/*AUTOSENSE*/frun or wIMM or wOPC or wRA or wRB or wRD)
if (frun) begin
xOPC <= wOPC;
xRD <= wRD;
@@ -130,7 +133,7 @@
xRB <= wRB;
xIMM <= wIMM;
end else begin
- xOPC <= 6'o44;
+ xOPC <= 6'o40;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xIMM <= 16'h0;
@@ -344,7 +347,8 @@
This controls the generation of the BRANCH, DELAY and LINK
signals.
*/
- wire fXCE = |rFSM;
+
+ wire fXCE = rFSM[2];
reg rBRA, rDLY, rLNK, xBRA, xDLY, xLNK;
always @(/*AUTOSENSE*/drun or rBCC or rMXBRA or rMXDLY or rMXLNK)
if (drun) begin
@@ -418,7 +422,18 @@
xDWBWE <= 1'h0;
// End of automatics
end
+
+
+ /**
+ Atomicity Check
+ ---------------
+ Checks that the current instruction being executed is ATOMIC
+ */
+ wire fATOM = ~(({wOPC[5:4],wOPC[2:1]} == 4'b1011) | (wOPC == 6'o55)
| (wOPC == 6'o54) );
+ reg [1:0] rATOM;
+
+
// PIPELINE REGISTERS ///////////////////////////////////////////////
always @(negedge nclk)
@@ -426,6 +441,7 @@
//rOPC <= 6'o40;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
+ rATOM <= 2'h0;
rBRA <= 1'h0;
rDLY <= 1'h0;
rDWBSTB <= 1'h0;
@@ -450,6 +466,8 @@
rSIMM <= 32'h0;
// End of automatics
end else if (prun) begin // if (prst)
+ rATOM <= #1 {rATOM[0], fATOM};
+
rIMM <= #1 xIMM;
rOPC <= #1 xOPC;
rRA <= #1 xRA;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
2007-10-28 22:19:09 UTC (rev 6722)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
2007-10-28 22:32:17 UTC (rev 6723)
@@ -66,7 +66,7 @@
// Internal
output [31:0] rPC;
output rIWBSTB;
- input [1:0] rFSM;
+ input [2:0] rFSM;
input rBRA;
input [31:0] rRESULT;
@@ -86,13 +86,14 @@
begin
// PC Sources - ALU, Direct, Next
case (rFSM)
- 2'b01: xIWBADR <= 32'h00000010; // HWINT
- //2'b10: xIWBADR <= 32'h00000020; // HWEXC
- //2'b11: xIWBADR <= #1 32'h00000008; // SWEXC
+ 3'o4: xIWBADR <= 32'h00000010; // HWINT
default: xIWBADR <= (rBRA) ? rRESULT : wPCNXT;
endcase // case (rFSM)
-
- xPC <= {rIWBADR[31:2],2'd0};
+
+ case (rFSM)
+ 3'o2: xPC <= (rBRA) ? rRESULT : {rIWBADR[31:2],2'd0};
+ default: xPC <= {rIWBADR[31:2],2'd0};
+ endcase // case (rFSM)
end // always @ (...
// PIPELINE REGISTERS //////////////////////////////////////////////////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-10-28 22:19:09 UTC (rev 6722)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-10-28 22:32:17 UTC (rev 6723)
@@ -106,7 +106,7 @@
input rDWBSTB, rDWBWE;
input [4:0] rRA, rRB, rRD;
input [31:0] rRESULT;
- input [1:0] rFSM;
+ input [2:0] rFSM;
input [31:0] rPC;
input [5:0] rOPC;
input [3:0] rDWBSEL;
@@ -128,11 +128,10 @@
always @(/*AUTOSENSE*/rFSM or rPC or rRD) begin
xPC_ <= rPC[31:2];
- xINT <= (rFSM != 2'o0);
+ xINT <= (rFSM[2]);
case (rFSM)
- 2'o1: xRD_ <= 5'd14; // HWINT
- //2'o2: xRD_ <= 5'd17; // HWEXC
+ 3'o4: xRD_ <= 5'd14; // HWINT
default: xRD_ <= rRD;
endcase // case (rFSM)
end
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matt <=