[Commit-gnuradio] r6722 - in gnuradio/branches/developers/matt/u2f: sdr_lib top/u2_basic

[matt]

Author: matt
Date: 2007-10-28 16:19:09 -0600 (Sun, 28 Oct 2007)
New Revision: 6722

Modified:
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
   gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
   gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
mostly done tx inband signaling, partially done rx


Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-10-28 
22:18:22 UTC (rev 6721)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-10-28 
22:19:09 UTC (rev 6722)
@@ -7,8 +7,7 @@
    input [13:0] adc_a, input adc_ovf_a,
    input [13:0] adc_b, input adc_ovf_b,
    
-   output [15:0] bb_i,
-   output [15:0] bb_q,
+   output [31:0] sample,
    input run_rx,
    output wr_req
    );
@@ -19,11 +18,10 @@
 
    wire [23:0] i_decim, q_decim;
    wire [7:0]  decim_rate;
-   wire        stb_decim;
    
-   assign bb_i = i_decim[23:8];
-   assign bb_q = q_decim[23:8];
+   assign      sample = {i_decim[23:8],q_decim[23:8]};
 
+   wire        stb_decim;
    assign wr_req = stb_decim;
    
    setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0

Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v  2007-10-28 
22:18:22 UTC (rev 6721)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v  2007-10-28 
22:19:09 UTC (rev 6722)
@@ -19,16 +19,34 @@
      input wr_full_i,
      
      // From DSP Core
-     input [15:0] bb_i,
-     input [15:0] bb_q,
+     input [31:0] sample,
      output run_rx,
      input wr_req     
      );
 
-   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(run_rx),.changed());
+
+   wire [31:0] new_time, new_command;
+   wire        store_command;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+4)) sr_4
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(new_time),.changed(store_command));
    
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+5)) sr_5
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(new_command),.changed());
+
+   wire [31:0] rcvtime;
+   wire [8:0]  lines_per_frame;
+   wire [22:0] numlines;
+   
+   shortfifo #(.WIDTH(64)) commandfifo
+     (.clk(clk),.rst(rst),
+      .datain({new_time,new_command}), .write(store_command), .full(full_ctrl),
+      .dataout({rcvtime,numlines,lines_per_frame}), .read(read_ctrl), 
.empty(empty_ctrl) );
+
    // Buffer interface to internal FIFO
    wire    write, full, read, empty;
    reg            xfer_active;
@@ -62,7 +80,7 @@
    // Internal FIFO, size 9 is 2K, size 10 is 4K
    longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo
      (.clk(clk),.rst(rst),
-      .datain({sop_i,eop_i,bb_i,bb_q}), .write(write), .full(full),
+      .datain({sop_i,eop_i,sample}), .write(write), .full(full),
       .dataout({sop_o,eop_o,wr_dat_o}), .read(read), .empty(empty)
       );
 

Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v  2007-10-28 
22:18:22 UTC (rev 6721)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v  2007-10-28 
22:19:09 UTC (rev 6722)
@@ -26,8 +26,9 @@
    // Buffer interface to internal FIFO
    wire     write_data, write_ctrl, full_data, full_ctrl;
    wire     read_data, read_ctrl, empty_data, empty_ctrl;
+   wire     clear_state;
    reg [1:0] xfer_state;
-   reg [1:0] held_flags;
+   reg [2:0] held_flags;
    
    localparam XFER_IDLE = 0;
    localparam XFER_1 = 1;
@@ -45,7 +46,7 @@
         XFER_1 :
           begin
              xfer_state <= XFER_2;
-             held_flags <= rd_dat_i[1:0];
+             held_flags <= rd_dat_i[2:0];
           end
         XFER_2 :
           if(~full_ctrl)
@@ -60,10 +61,10 @@
 
    assign rd_read_o = (xfer_state == XFER_1) | write_data | write_ctrl;
    assign rd_done_o = 0;  // Always take everything we're given
-   assign rd_error_o = 0;  // Don't anticipate any errors here
+   assign rd_error_o = 0;  // Should we indicate overruns here?
    
    wire [31:0] data_o;
-   wire        sop_o, eop_o, eob, sob;
+   wire        sop_o, eop_o, eob, sob, send_imm;
    wire [31:0] sendtime;
    
    longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) txfifo
@@ -71,24 +72,23 @@
       .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write_data), 
.full(full_data),
       .dataout({sop_o,eop_o,data_o}), .read(read_data), .empty(empty_data) );
 
-   shortfifo #(.WIDTH(34)) ctrlfifo
+   shortfifo #(.WIDTH(35)) ctrlfifo
      (.clk(clk),.rst(rst),
-      .datain({held_flags[1:0],rd_dat_i}), .write(write_ctrl), 
.full(full_ctrl),
-      .dataout({sob,eob,sendtime}), .read(read_ctrl), .empty(empty_ctrl) );
+      .datain({held_flags[2:0],rd_dat_i}), .write(write_ctrl), 
.full(full_ctrl),
+      .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), 
.empty(empty_ctrl) );
 
    // Internal FIFO to DSP interface
    reg [2:0]   ibs_state;
    
    localparam  IBS_IDLE = 0;
-   localparam  IBS_HAVE_FLAGS = 1;
-   localparam  IBS_HAVE_TIME = 2;
-   localparam  IBS_WAIT = 3;
-   localparam  IBS_RUNNING = 4;
-   localparam  IBS_CONT_BURST = 5;
-   localparam  IBS_LAST_ONE = 6;
+   localparam  IBS_WAIT = 1;
+   localparam  IBS_RUNNING = 2;
+   localparam  IBS_CONT_BURST = 3;
    localparam  IBS_UNDERRUN = 7;
 
-   wire        too_late = 0;
+   wire [32:0] delta_time = {1'b0,sendtime}-{1'b0,master_time};
+   
+   wire        too_late = (delta_time[32:31] == 2'b11);
    wire        go_now = ( master_time == sendtime );
    
    always @(posedge clk)
@@ -100,7 +100,9 @@
           if(~empty_ctrl)
             ibs_state <= IBS_WAIT;
         IBS_WAIT :
-          if(too_late)
+          if(send_imm)
+            ibs_state <= IBS_RUNNING;
+          else if(too_late)
             ibs_state <= IBS_UNDERRUN;
           else if(go_now)
             ibs_state <= IBS_RUNNING;
@@ -118,6 +120,9 @@
             ibs_state <= IBS_RUNNING;
           else if(strobe)
             ibs_state <= IBS_UNDERRUN;
+        IBS_UNDERRUN :   // FIXME Should probably clean everything out
+          if(clear_state)
+            ibs_state <= IBS_IDLE;
        endcase // case(ibs_state)
 
    assign      read_ctrl = (ibs_state == IBS_RUNNING) & strobe & eop_o;  // & 
~empty_ctrl;
@@ -126,6 +131,10 @@
    assign      underrun = (ibs_state == IBS_UNDERRUN);
 
    wire [7:0]  interp_rate;
+   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_state));
+
    setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(interp_rate),.changed());

Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-10-28 22:18:22 UTC (rev 6721)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-10-28 22:19:09 UTC (rev 6722)
@@ -434,8 +434,7 @@
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
    reg                  adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, 
adc_ovf_b_reg2;
 
-   wire [31:0]          sample_tx;
-   wire [15:0]          bb_i_rx, bb_q_rx;
+   wire [31:0]          sample_rx, sample_tx;
    wire         run_rx, run_tx;
    wire         wr_req, strobe_tx;
    
@@ -457,13 +456,13 @@
       .master_time(master_time),.overrun(overrun),
       .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), 
.wr_error_o(wr1_error),
       .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
-      .bb_i(bb_i_rx), .bb_q(bb_q_rx), .run_rx(run_rx), .wr_req(wr_req) );
+      .sample(sample_rx), .run_rx(run_rx), .wr_req(wr_req) );
    
    dsp_core_rx dsp_core_rx
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
-      .bb_i(bb_i_rx), .bb_q(bb_q_rx), .run_rx(run_rx), .wr_req(wr_req) );
+      .sample(sample_rx), .run_rx(run_rx), .wr_req(wr_req) );
 
    tx_control tx_control
      (.clk(dsp_clk), .rst(dsp_rst),