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[Commit-gnuradio] r6608 - gnuradio/branches/developers/matt/u2f/sdr_lib
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From: |
matt |
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Subject: |
[Commit-gnuradio] r6608 - gnuradio/branches/developers/matt/u2f/sdr_lib |
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Date: |
Wed, 10 Oct 2007 01:15:46 -0600 (MDT) |
Author: matt
Date: 2007-10-10 01:15:46 -0600 (Wed, 10 Oct 2007)
New Revision: 6608
Modified:
gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
Log:
basically working IBS. Needs recovery from underruns
Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-10-10
07:13:54 UTC (rev 6607)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-10-10
07:15:46 UTC (rev 6608)
@@ -9,18 +9,20 @@
output reg [15:0] dac_b,
// To tx_control
- input [15:0] bb_i,
- input [15:0] bb_q,
- input run_tx,
- output rd_ack // asserting rd_ack means "I got it, send the next one"
+ input [31:0] sample,
+ input run,
+ input strobe
);
wire [15:0] i, q, scale_i, scale_q;
wire [31:0] phase_inc;
reg [31:0] phase;
wire [7:0] interp_rate;
- wire stb_interp;
-
+
+ setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(interp_rate),.changed());
+
setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
@@ -29,40 +31,33 @@
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({scale_i,scale_q}),.changed());
- setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
- (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(interp_rate),.changed());
-
- strobe_gen
strobe_gen(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
- .strobe_in(run_tx),.strobe(stb_interp) );
-
- assign rd_ack = stb_interp;
-
always @(posedge clk)
if(rst)
phase <= 0;
- else if(run_tx)
+ else if(run)
phase <= phase + phase_inc;
wire signed [15:0] da, db;
reg signed [15:0] dar, dbr;
wire signed [35:0] prod_i, prod_q;
-
+
+ wire [15:0] bb_i = sample[31:16];
+ wire [15:0] bb_q = sample[15:0];
wire [15:0] i_interp, q_interp;
cic_interp #(.bw(16),.N(4),.log2_of_max_rate(7))
- cic_interp_i(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
- .strobe_in(stb_interp),.strobe_out(1),
+ cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+ .strobe_in(strobe),.strobe_out(1),
.signal_in(bb_i),.signal_out(i_interp));
cic_interp #(.bw(16),.N(4),.log2_of_max_rate(7))
- cic_interp_q(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
- .strobe_in(stb_interp),.strobe_out(1),
+ cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+ .strobe_in(strobe),.strobe_out(1),
.signal_in(bb_q),.signal_out(q_interp));
cordic #(.bitwidth(16),.zwidth(16))
- cordic(.clock(clk), .reset(rst), .enable(run_tx),
+ cordic(.clock(clk), .reset(rst), .enable(run),
.xi(i_interp),.yi(q_interp),.zi(phase[31:16]),
.xo(da),.yo(db),.zo() );
Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v 2007-10-10
07:13:54 UTC (rev 6607)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v 2007-10-10
07:15:46 UTC (rev 6608)
@@ -24,41 +24,60 @@
);
// Buffer interface to internal FIFO
- wire write, full, read, empty;
- reg xfer_active;
+ wire write_data, write_ctrl, full_data, full_ctrl;
+ wire read_data, read_ctrl, empty_data, empty_ctrl;
+ reg [1:0] xfer_state;
+ reg [1:0] held_flags;
+
+ localparam XFER_IDLE = 0;
+ localparam XFER_1 = 1;
+ localparam XFER_2 = 2;
+ localparam XFER_DATA = 3;
+
always @(posedge clk)
if(rst)
- xfer_active <= 0;
- else if(rd_eop_i & ~full) // In case the last line can't be stored right
away
- xfer_active <= 0;
- else if(rd_sop_i)
- xfer_active <= 1;
+ xfer_state <= XFER_IDLE;
+ else
+ case(xfer_state)
+ XFER_IDLE :
+ if(rd_sop_i)
+ xfer_state <= XFER_1;
+ XFER_1 :
+ begin
+ xfer_state <= XFER_2;
+ held_flags <= rd_dat_i[1:0];
+ end
+ XFER_2 :
+ if(~full_ctrl)
+ xfer_state <= XFER_DATA;
+ XFER_DATA :
+ if(rd_eop_i & ~full_data)
+ xfer_state <= XFER_IDLE;
+ endcase // case(xfer_state)
- assign write = xfer_active & ~full;
+ assign write_data = (xfer_state == XFER_DATA) & ~full_data;
+ assign write_ctrl = (xfer_state == XFER_2) & ~full_ctrl;
+
+ assign rd_read_o = (xfer_state == XFER_1) | write_data | write_ctrl;
+ assign rd_done_o = 0; // Always take everything we're given
+ assign rd_error_o = 0; // Don't anticipate any errors here
- assign rd_read_o = write;
- assign rd_done_o = 0; // Always take everything we're given
- assign rd_error_o = 0; // Don't anticipate any errors here
-
- // Internal FIFO, size 9 is 2K, size 10 is 4K
- wire sop_o, eop_o;
wire [31:0] data_o;
+ wire sop_o, eop_o, eob, sob;
+ wire [31:0] sendtime;
longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) txfifo
(.clk(clk),.rst(rst),
- .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
- .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty)
- );
+ .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write_data),
.full(full_data),
+ .dataout({sop_o,eop_o,data_o}), .read(read_data), .empty(empty_data) );
+ shortfifo #(.WIDTH(34)) ctrlfifo
+ (.clk(clk),.rst(rst),
+ .datain({held_flags[1:0],rd_dat_i}), .write(write_ctrl),
.full(full_ctrl),
+ .dataout({sob,eob,sendtime}), .read(read_ctrl), .empty(empty_ctrl) );
+
// Internal FIFO to DSP interface
- reg [31:0] next_time;
- reg next_time_valid;
- reg [31:0] next_sample;
- reg next_sample_valid;
- reg [31:0] next_flags;
- reg next_flags_valid;
reg [2:0] ibs_state;
- reg next_eop;
localparam IBS_IDLE = 0;
localparam IBS_HAVE_FLAGS = 1;
@@ -66,50 +85,20 @@
localparam IBS_WAIT = 3;
localparam IBS_RUNNING = 4;
localparam IBS_CONT_BURST = 5;
- localparam IBS_CONT_BURST2 = 6;
+ localparam IBS_LAST_ONE = 6;
localparam IBS_UNDERRUN = 7;
wire too_late = 0;
- wire go_now = ( master_time == next_time );
- wire eob = next_flags[0];
- wire sob = next_flags[1];
+ wire go_now = ( master_time == sendtime );
always @(posedge clk)
if(rst)
- begin
- ibs_state <= IBS_IDLE;
- next_time_valid <= 0;
- next_sample_valid <= 0;
- next_flags_valid <=0;
- end
+ ibs_state <= IBS_IDLE;
else
case(ibs_state)
IBS_IDLE :
- if(~empty & sop_o)
- begin
- ibs_state <= IBS_HAVE_FLAGS;
- next_flags <= data_o;
- next_flags_valid <= 1;
- end
- else
- next_flags_valid <= 0;
- IBS_HAVE_FLAGS :
- if(~sob)
- ibs_state <= IBS_UNDERRUN;
- else if(~empty)
- begin
- ibs_state <= IBS_HAVE_TIME;
- next_time <= data_o;
- next_time_valid <= 1;
- end
- IBS_HAVE_TIME :
- if(~empty)
- begin
- ibs_state <= IBS_WAIT;
- next_sample <= data_o;
- next_eop <= eop_o;
- next_sample_valid <= 1;
- end
+ if(~empty_ctrl)
+ ibs_state <= IBS_WAIT;
IBS_WAIT :
if(too_late)
ibs_state <= IBS_UNDERRUN;
@@ -117,55 +106,23 @@
ibs_state <= IBS_RUNNING;
IBS_RUNNING :
if(strobe)
- if(~next_sample_valid)
+ if(empty_data)
ibs_state <= IBS_UNDERRUN;
- else
- if(next_eop & eob)
+ else if(eop_o)
+ if(eob)
ibs_state <= IBS_IDLE;
- else if(next_eop)
- ibs_state <= IBS_CONT_BURST;
- else if(~empty)
- begin
- next_sample <= data_o;
- next_eop <= eop_o;
- end
else
- next_sample <= 0;
- else
- if(~empty & ~next_sample_valid)
- begin
- next_sample <= data_o;
- next_eop <= eop_o;
- next_sample_valid <= 1;
- end
+ ibs_state <= IBS_CONT_BURST;
IBS_CONT_BURST :
- if(strobe)
+ if(~empty_ctrl) // & ~empty_data)
+ ibs_state <= IBS_RUNNING;
+ else if(strobe)
ibs_state <= IBS_UNDERRUN;
- else if(~empty & sop_o)
- begin
- ibs_state <= IBS_CONT_BURST2;
- next_flags <= data_o;
- end
- IBS_CONT_BURST2 :
- if(strobe)
- ibs_state <= IBS_UNDERRUN;
- else if(sob)
- ibs_state <= IBS_UNDERRUN;
- else if(~empty)
- begin
- ibs_state <= IBS_RUNNING;
- next_sample_valid <= 0;
- end
- IBS_UNDERRUN :
- // clear out junk
- ;
endcase // case(ibs_state)
-
- assign run = ((ibs_state == IBS_RUNNING) |
- (ibs_state == IBS_CONT_BURST) |
- (ibs_state==IBS_CONT_BURST2));
- assign waiting = (ibs_state == IBS_WAIT);
- assign read = ~empty & ~waiting & ~(run & ~strobe);
+
+ assign read_ctrl = (ibs_state == IBS_RUNNING) & strobe & eop_o; // &
~empty_ctrl;
+ assign read_data = (ibs_state == IBS_RUNNING) & strobe & ~empty_data;
+ assign run = (ibs_state == IBS_RUNNING) | (ibs_state ==
IBS_CONT_BURST);
assign underrun = (ibs_state == IBS_UNDERRUN);
wire [7:0] interp_rate;
@@ -176,5 +133,5 @@
strobe_gen
strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
.strobe_in(run),.strobe(strobe) );
- assign sample = next_sample;
+ assign sample = data_o;
endmodule // tx_control
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