[Commit-gnuradio] r6607 - gnuradio/branches/developers/matt/u2f/firmware

[matt]

Author: matt
Date: 2007-10-10 01:13:54 -0600 (Wed, 10 Oct 2007)
New Revision: 6607

Added:
   gnuradio/branches/developers/matt/u2f/firmware/ibs_tx_test.c
Modified:
   gnuradio/branches/developers/matt/u2f/firmware/Makefile
Log:
test the new ibs on TX


Modified: gnuradio/branches/developers/matt/u2f/firmware/Makefile
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/Makefile     2007-10-10 
07:13:33 UTC (rev 6606)
+++ gnuradio/branches/developers/matt/u2f/firmware/Makefile     2007-10-10 
07:13:54 UTC (rev 6607)
@@ -20,8 +20,8 @@
 
 .PRECIOUS : %.bin
 
-ROMS = test1.rom eth_test.rom timer_test.rom
-DUMPS = test1.dump eth_test.dump timer_test.dump
+ROMS = test1.rom eth_test.rom timer_test.rom ibs_tx_test.rom
+DUMPS = test1.dump eth_test.dump timer_test.dump ibs_tx_test.dump
 LIBS = libu2fw.a
 
 all: $(ROMS) $(DUMPS)
@@ -48,6 +48,9 @@
 timer_test.exe:  timer_test.o libu2fw.a
        $(CC) $(LDFLAGS) $^ -o $@
 
+ibs_tx_test.exe:  ibs_tx_test.o libu2fw.a
+       $(CC) $(LDFLAGS) $^ -o $@
+
 clean:
        rm -f *.a *.o *.bin *.rom *.exe *.dump
 
@@ -59,5 +62,6 @@
 sim_io.o: sim_io.h
 test1_main.o: u2_init.h memory_map.h eth_mac_regs.h spi.h buffer_pool.h 
sim_io.h test1_main.c
 eth_test.o: u2_init.h memory_map.h eth_mac_regs.h spi.h buffer_pool.h sim_io.h 
eth_test.c
+ibs_tx_test.o: u2_init.h memory_map.h eth_mac_regs.h spi.h buffer_pool.h 
sim_io.h ibs_tx_test.c
 eth.o: u2_init.h memory_map.h eth_mac_regs.h spi.h buffer_pool.h sim_io.h eth.c
 eth_mac.o: memory_map.h eth_mac_regs.h eth_mac.c

Added: gnuradio/branches/developers/matt/u2f/firmware/ibs_tx_test.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/ibs_tx_test.c                
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/firmware/ibs_tx_test.c        
2007-10-10 07:13:54 UTC (rev 6607)
@@ -0,0 +1,141 @@
+#include "u2_init.h"
+#include "memory_map.h"
+#include "spi.h"
+#include "sim_io.h"
+#include "buffer_pool.h"
+
+// Globals
+#define EMPTY 0
+#define FILLING 1
+#define FULL 2
+#define EMPTYING 3
+
+#define PORT 2    // ethernet = 2, serdes = 0
+int dsp_rx_buf, dsp_tx_buf, serdes_rx_buf, serdes_tx_buf;
+int dsp_rx_idle, dsp_tx_idle, serdes_rx_idle, serdes_tx_idle;
+
+int buffer_state[4];
+
+static void
+wait_until_status_nonzero(void)
+{
+  while (buffer_pool_status->status == 0)
+    ;
+}
+
+int
+main(void)
+{
+  int i;
+  
+  u2_init();
+  
+  dsp_tx_regs->freq = 0;
+  dsp_tx_regs->scale_i = 1;
+  dsp_tx_regs->scale_q = 1;
+  dsp_tx_regs->interp_rate = 7;
+
+  // Write data to be sent into the first buffer
+  volatile unsigned int *buffer0 = buffer_ram(0);
+  volatile unsigned int *buffer1 = buffer_ram(1);
+  
+
+  sim_puts("Starting to fill in RAM\n");
+  for(i=0;i<512;i++) 
+    buffer0[i] = i;
+  sim_puts("Filled in RAM\n");
+  
+  buffer0[0] = 3; // start and end of buffer
+  buffer0[1] = 0x8000;  // start time
+  bp_send_from_buf(0, 1, 1, 0, 9);
+  while (buffer_pool_status->status == 0)
+    ;
+  while(timer_regs -> time < 0x8400)
+    {}
+
+  buffer0[0] = 3; // start and end of buffer
+  buffer0[1] = 0x8800;  // start time
+  bp_clear_buf(0);
+  bp_send_from_buf(0, 1, 1, 0, 9);
+  while (buffer_pool_status->status == 0)
+    ;
+  while(timer_regs -> time < 0x9000)
+    {}
+
+  buffer0[0] = 0x2;  // not last
+  buffer0[1] = 0x9100;  // start time
+  bp_clear_buf(0);
+  bp_send_from_buf(0, 1, 1, 0, 9);
+  while (buffer_pool_status->status == 0)
+    ;
+  buffer0[0] = 0x1;  // last
+  buffer0[1] = 0x0000;  // start time
+  bp_clear_buf(0);
+  bp_send_from_buf(0, 1, 1, 0, 9);
+  while (buffer_pool_status->status == 0)
+    ;
+
+  buffer0[0] = 0x2; // not last
+  buffer0[1] = 0x9600;  // start time
+  bp_clear_buf(0);
+  bp_send_from_buf(0, 1, 1, 0, 9);
+  while (buffer_pool_status->status == 0)
+    ;
+
+
+  while(timer_regs -> time < 0xa000)
+    {}
+
+  sim_puts("Done\n");
+
+  while(1)
+    {}
+  sim_finish();
+  
+  // Send a bunch, let them pile up in FIFO
+  bp_send_from_buf(0, 2, 1, 21, 80);    wait_until_status_nonzero();
+  bp_clear_buf(0);
+  sim_puts("First add'l TX done\n");
+  bp_send_from_buf(0, 2, 1, 81, 288);   wait_until_status_nonzero();
+  bp_clear_buf(0);
+  bp_send_from_buf(0, 2, 1, 289, 292);  wait_until_status_nonzero();
+  bp_clear_buf(0);
+  bp_send_from_buf(0, 2, 1, 293, 326);  wait_until_status_nonzero();
+  bp_clear_buf(0);
+  bp_send_from_buf(0, 2, 1, 327, 399);  wait_until_status_nonzero();
+  bp_clear_buf(0);
+  bp_send_from_buf(0, 2, 1, 400, 511);  wait_until_status_nonzero();
+  bp_clear_buf(0);
+  sim_puts("All add'l TX done\n");
+  
+  bp_receive_to_buf(1, 2, 1, 21, 80);   wait_until_status_nonzero();
+  bp_clear_buf(1);
+  sim_puts("First add'l RX done\n");
+  bp_receive_to_buf(1, 2, 1, 81, 288);  wait_until_status_nonzero();
+  bp_clear_buf(1);
+  bp_receive_to_buf(1, 2, 1, 289, 292); wait_until_status_nonzero();
+  bp_clear_buf(1);
+  bp_receive_to_buf(1, 2, 1, 293, 326); wait_until_status_nonzero();
+  bp_clear_buf(1);
+  bp_receive_to_buf(1, 2, 1, 327, 399); wait_until_status_nonzero();
+  bp_clear_buf(1);
+  bp_receive_to_buf(1, 2, 1, 400, 511); wait_until_status_nonzero();
+  bp_clear_buf(1);
+  sim_puts("All add'l RX done\n");
+
+  for(i=0;i<512;i++)
+    if(buffer0[i] != buffer1[i]) {
+      sim_puts("ERROR at location: ");
+      sim_puthex_nl(i);
+      sim_puts("Value sent: ");
+      sim_puthex_nl(buffer0[i]);
+      sim_puts("Value rcvd: ");
+      sim_puthex_nl(buffer1[i]);
+      //break;
+    }
+  
+  sim_puts("Done Testing\n");
+  
+  sim_finish();
+  return 1;
+}