[Commit-gnuradio] r6524 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-09-24 17:25:38 -0600 (Mon, 24 Sep 2007)
New Revision: 6524

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
added pic and timer, connected interrupts


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-09-24 23:24:28 UTC (rev 6523)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-09-24 23:25:38 UTC (rev 6524)
@@ -135,22 +135,24 @@
    
    wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, 
s2_dat_i, s3_dat_i,
-                s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, 
s6_dat_i, s7_dat_i;
-   wire [aw-1:0] m0_adr, m1_adr, 
s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
-   wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, 
s5_sel, s6_sel, s7_sel;
-   wire         m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, 
s5_ack, s6_ack, s7_ack;
-   wire         m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, 
s5_stb, s6_stb, s7_stb;
-   wire         m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, 
s5_cyc, s6_cyc, s7_cyc;
-   wire         m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, 
s5_err, s6_err, s7_err;
-   wire         m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, 
s5_rty, s6_rty, s7_rty;
-   wire         m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, 
s7_we;
+                s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, 
s6_dat_i, s7_dat_i,
+                s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i;
+   wire [aw-1:0] m0_adr, m1_adr, 
s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr;
+   wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, 
s5_sel, s6_sel, s7_sel, s8_sel, s9_sel;
+   wire         m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, 
s5_ack, s6_ack, s7_ack, s8_ack, s9_ack;
+   wire         m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, 
s5_stb, s6_stb, s7_stb, s8_stb, s9_stb;
+   wire         m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, 
s5_cyc, s6_cyc, s7_cyc, s8_cyc, s9_cyc;
+   wire         m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, 
s5_err, s6_err, s7_err, s8_err, s9_err;
+   wire         m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, 
s5_rty, s6_rty, s7_rty, s8_rty, s9_rty;
+   wire         m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, 
s7_we, s8_we, s9_we;
    
    wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01),
-               
.s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010),
-               .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101),
+               
.s215_addr_w(5),.s2_addr(5'b10000),.s3_addr(5'b10010),.s4_addr(5'b10100),
+               
.s5_addr(5'b10110),.s6_addr(5'b11000),.s7_addr(5'b11010),.s8_addr(5'b11100),.s9_addr(5'b11101),
+               
.s10_addr(5'b11111),.s11_addr(5'b11111),.s12_addr(5'b11111),.s13_addr(5'b11111),
+               .s14_addr(5'b11111),.s15_addr(5'b11111),
                .dw(dw),.aw(aw),.sw(sw)) wb_1master
-     (.clk_i(wb_clk),.rst_i(wb_rst),
-      
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
       
.m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
       
.m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
       .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o 
(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
@@ -168,8 +170,17 @@
       .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o 
(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
       
.s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
       .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o 
(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
-      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
-      );
+      
.s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty),
+      .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o 
(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      
.s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
+      .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o 
(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      
.s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
+      .s10_dat_i(0),.s10_ack_i(0),.s10_err_i(0),.s10_rty_i(0),
+      .s11_dat_i(0),.s11_ack_i(0),.s11_err_i(0),.s11_rty_i(0),
+      .s12_dat_i(0),.s12_ack_i(0),.s12_err_i(0),.s12_rty_i(0),
+      .s13_dat_i(0),.s13_ack_i(0),.s13_err_i(0),.s13_rty_i(0),
+      .s14_dat_i(0),.s14_ack_i(0),.s14_err_i(0),.s14_rty_i(0),
+      .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0)  );
    
    
//////////////////////////////////////////////////////////////////////////////////////////
    // Reset Controller
@@ -185,7 +196,7 @@
    wire [aw-1:0] iram_wr_adr, iram_rd_adr;
    wire [dw-1:0] iram_wr_dat, iram_rd_dat;
 
-   wire         bus_error, proc_int;
+   wire         bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int;
 
    assign       iram_rd_ack = ram_loader_done ? iram_ack : 1'b0;
    assign       iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack;
@@ -255,7 +266,7 @@
    
       .stream_clk(dsp_clk), .stream_rst(dsp_rst),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .status(status),.sys_int_o(proc_int),
+      .status(status),.sys_int_o(buffer_int),
 
       .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
       .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
@@ -285,7 +296,7 @@
      
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
       
.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),
 
-      .wb_err_o(s2_err),.wb_int_o(s2_int),
+      .wb_err_o(s2_err),.wb_int_o(spi_int),
       
.ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
       .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
 
@@ -296,7 +307,7 @@
      i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
          
.wb_adr_i(s3_adr[2:0]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
          .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
-         .wb_ack_o(s3_ack),.wb_inta_o(s3_int),
+         .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
          
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
          
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
 
@@ -379,7 +390,7 @@
                                      .in(set_data),.out(misc_outs),.changed());
 
    // /////////////////////////////////////////////////////////////////////////
-   // Ethernet MAC
+   // Ethernet MAC  Slave #6
    
    wire         Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
    wire         Rx_mac_ra, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_pa, 
Rx_mac_err;
@@ -418,17 +429,28 @@
       .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
       .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop) );
 
+   // /////////////////////////////////////////////////////////////////////////
+   // Interrupt Controller, Slave #8
+   
+   simple_pic simple_pic
+     
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[1:0]),
+      
.we_i(s8_we),.dat_i(s8_dat_o[7:0]),.dat_o(s8_dat_i[7:0]),.ack_o(s8_ack),.int_o(proc_int),
+      .irq({3'b000,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}) );
+   assign       s8_dat_i[31:8] = 0;
+        
+   // /////////////////////////////////////////////////////////////////////////
+   // Master Timer, Slave #9
 
+   wire [31:0]          master_time;
+   timer timer
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[2:0]),
+      .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
+      .sys_clk_i(dsp_clk),.master_time_o(master_time),.int_o(timer_int) );
+   
    // /////////////////////////////////////////////////////////////////////////
    // DSP
 
-   reg [31:0]   master_time;
-   always @(posedge dsp_clk)
-     if(dsp_rst)
-       master_time <= 0;
-     else
-       master_time <= master_time + 1;
-   
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
    reg                  adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, 
adc_ovf_b_reg2;