[Commit-gnuradio] r6516 - gnuradio/branches/developers/matt/u2f/eth/rtl/verilog

[matt]

Author: matt
Date: 2007-09-24 01:40:42 -0600 (Mon, 24 Sep 2007)
New Revision: 6516

Added:
   gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/elastic_buffer.v
   gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/elastic_buffer_tb.v
Log:
attempt to reduce clocks


Added: gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/elastic_buffer.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/elastic_buffer.v      
                        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/elastic_buffer.v      
2007-09-24 07:40:42 UTC (rev 6516)
@@ -0,0 +1,80 @@
+
+
+module elastic_buffer
+  ( input rx_clk,
+    input tx_clk,
+    input rst,
+    
+    input [7:0] rxd,
+    input      rx_dv,
+    input      rx_er,
+    input      crs,
+    input      col,
+    
+    output [7:0] rxd_ret,
+    output reg  rx_dv_ret,
+    output      rx_er_ret,
+    output      crs_ret,
+    output      col_ret );
+
+   reg [3:0]    
addr_wr,addr_wr_gray,awg_d1,awg_d2,addr_wr_gray_ret,awgr_d1,addr_wr_ungray,addr_rd;
+   
+   reg [11:0]   buffer [0:15];
+   
+   reg [7:0]    rxd_d1, rxd_d2;
+   reg                  rx_dv_d1,rx_er_d1,crs_d1,col_d1, 
rx_dv_d2,rx_er_d2,crs_d2,col_d2;               
+
+   always @(posedge rx_clk)
+     {col_d1,crs_d1,rx_er_d1,rx_dv_d1,rxd_d1} <= {col,crs,rx_er,rx_dv,rxd};
+
+   always @(posedge rx_clk)
+     {col_d2,crs_d2,rx_er_d2,rx_dv_d2,rxd_d2} <= 
{col_d1,crs_d1,rx_er_d1,rx_dv_d1,rxd_d1};
+   
+   always @(posedge rx_clk)
+     buffer[addr_wr] <= {col_d2,crs_d2,rx_er_d2,rx_dv_d1,rxd_d2};
+   
+   always @(posedge rx_clk or posedge rst)
+     if(rst) addr_wr <= 0;
+     else addr_wr <= addr_wr + 1;
+   
+   always @(posedge rx_clk)
+     begin
+       addr_wr_gray <= {addr_wr[3],^addr_wr[3:2],^addr_wr[2:1],^addr_wr[1:0]};
+       awg_d1 <= addr_wr_gray;
+       awg_d2 <= awg_d1;
+     end
+   
+   always @(posedge tx_clk)
+     begin
+       addr_wr_gray_ret <= awg_d2;
+       awgr_d1 <= addr_wr_gray_ret;
+       addr_wr_ungray <= 
{awgr_d1[3],^awgr_d1[3:2],^awgr_d1[3:1],^awgr_d1[3:0]};
+     end
+
+   wire [3:0] addr_delta = addr_rd-addr_wr_ungray;
+   
+   always @(posedge tx_clk)
+     if(rst)
+       addr_rd <= 0;
+     else if(buffer[addr_rd][8])
+       addr_rd <= addr_rd + 1;
+     else
+       case(addr_delta)
+        4'd1, 4'd2, 4'd3, 4'd4, 4'd5 : addr_rd <= addr_rd;
+        4'd15, 4'd14, 4'd13, 4'd12, 4'd11 : addr_rd <= addr_rd + 2;
+        default : addr_rd <= addr_rd + 1;
+       endcase // case(addr_delta)
+/*   
+  else if(addr_rd == (addr_wr_ungray + 4'd1))
+       ;
+     else if(addr_rd == (addr_wr_ungray - 4'd1))
+       addr_rd <= addr_rd + 2;
+     else
+       addr_rd <= addr_wr_ungray + 1;
+*/
+   wire         rx_dv_ret_adv;
+   assign       {col_ret,crs_ret,rx_er_ret,rx_dv_ret_adv,rxd_ret} = 
buffer[addr_rd];
+   always @(posedge tx_clk)
+     rx_dv_ret <= rx_dv_ret_adv;
+   
+endmodule // elastic_buffer

Added: gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/elastic_buffer_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/elastic_buffer_tb.v   
                        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/elastic_buffer_tb.v   
2007-09-24 07:40:42 UTC (rev 6516)
@@ -0,0 +1,62 @@
+
+module elastic_buffer_tb;
+
+   reg               rx_clk = 0, tx_clk = 0, rst = 1;
+
+   reg [7:0]  rxd;
+   wire [7:0] rxd_ret;
+   reg               rx_dv, rx_er, crs, col;
+   wire       rx_dv_ret, rx_er_ret, crs_ret, col_ret;
+   
+   elastic_buffer elastic_buffer
+     (.rx_clk(rx_clk),.tx_clk(tx_clk),.rst(rst),
+      .rxd(rxd),.rx_dv(rx_dv),.rx_er(rx_er),.crs(crs),.col(col),
+      .rxd_ret(rxd_ret),.rx_dv_ret(rx_dv_ret),.rx_er_ret(rx_er_ret),
+      .crs_ret(crs_ret),.col_ret(col_ret) );
+
+   always #100 rx_clk = ~rx_clk;
+   always #101 tx_clk = ~tx_clk;
+   initial #950 rst = 0;
+
+   initial    
+     begin
+       {col,crs,rx_er,rx_dv,rxd} <= 0;
+       @(negedge rst);
+       @(posedge rx_clk);
+
+       repeat (13)
+         begin
+            repeat (284)
+              @(posedge rx_clk);
+            SendPKT;
+         end
+       $finish;
+     end // initial begin
+
+   reg [7:0] rxd_ret_d1;
+   always @(posedge tx_clk)
+     rxd_ret_d1 <= rxd_ret;
+   
+   wire [7:0] diff = rxd_ret_d1 - rxd_ret;
+
+   task SendPKT;
+      begin
+        {col,crs,rx_er,rx_dv,rxd} <= 0;
+        @(posedge rx_clk);
+        {col,crs,rx_er,rx_dv,rxd} <= {4'hF,8'd1};
+        @(posedge rx_clk);
+        repeat (250)
+          begin
+             rxd <= rxd + 1;
+             @(posedge rx_clk);
+          end
+        {col,crs,rx_er,rx_dv,rxd} <= 0;
+        @(posedge rx_clk);
+      end
+   endtask // SendPKT
+          
+   initial begin
+      $dumpfile("elastic_buffer_tb.vcd");
+      $dumpvars(0,elastic_buffer_tb);
+   end
+endmodule // elastic_buffer_tb