[Commit-gnuradio] r6454 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-09-17 16:16:49 -0600 (Mon, 17 Sep 2007)
New Revision: 6454

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
Log:
reworked with new interface, seems to work 100%


Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v       
2007-09-17 22:14:59 UTC (rev 6453)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v       
2007-09-17 22:16:49 UTC (rev 6454)
@@ -21,24 +21,25 @@
 //  K30.7 111-11110
 
 module serdes_tx
-  (input clk,
-   input rst,
+  #(parameter FIFOSIZE = 9)
+    (input clk,
+     input rst,
+     
+     // TX HW Interface
+     output ser_tx_clk,
+     output reg [15:0] ser_t,
+     output reg ser_tklsb,
+     output reg ser_tkmsb,
+     
+     // TX Stream Interface
+     input [31:0] rd_dat_i,
+     output rd_read_o,
+     output rd_done_o,
+     output rd_error_o,
+     input rd_sop_i,
+     input rd_eop_i
+     );
    
-   // TX HW Interface
-   output ser_tx_clk,
-   output reg [15:0] ser_t,
-   output reg ser_tklsb,
-   output reg ser_tkmsb,
-
-   // TX Stream Interface
-   input [31:0] fifo_data_i,
-   output fifo_read_o,
-   output fifo_done_o,
-   output fifo_error_o,
-   input fifo_ready_i,
-   input fifo_empty_i
-   );
-
    localparam K_COMMA = 8'b101_11100;     // 0xBC K28.5
    localparam K_IDLE = 8'b001_11100;      // 0x3C K28.1
    localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
@@ -46,35 +47,57 @@
    localparam K_LOS = 8'b111_11111;       // 0xFF K31.7
    localparam K_ERROR = 8'b000_00000;     // 0x00 K00.0
    
-   assign ser_tx_clk = clk;
-
+   assign     ser_tx_clk = clk;
+   
    localparam IDLE = 3'd0;
-   localparam START = 3'd1;
-   localparam RUN1 = 3'd2;
-   localparam RUN2 = 3'd3;
-   localparam DONE = 3'd4;
+   localparam RUN1 = 3'd1;
+   localparam RUN2 = 3'd2;
+   localparam DONE = 3'd3;
+   localparam SENDCRC = 3'd4;
    localparam WAIT = 3'd5;
-   localparam SENDCRC = 3'd6;
    
-   reg [2:0]  state, next_state;
+   reg [2:0]  state;
    
    reg [15:0] CRC;
    wire [15:0] nextCRC;
    
-   // FIXME Implement sending of flow control if necessary
-
-   reg [15:0] second_word;
-   reg [33:0] pipeline;
-
+   
+   // Internal FIFO, size 9 is 2K, size 10 is 4K bytes
+   wire        sop_o, eop_o, write, full, read, empty;
+   wire [31:0] data_o;
+   reg                xfer_active;
+   
+   longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
+     (.clk(clk),.rst(rst),
+      .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
+      .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty) );
+   
+   // Buffer interface to internal FIFO
    always @(posedge clk)
      if(rst)
-       pipeline <= 34'd0;
-     else
-       pipeline <= {fifo_ready_i, fifo_empty_i, fifo_data_i};
-   wire       fifo_ready_d = pipeline[33];
-   wire       fifo_empty_d = pipeline[32];
-   wire [31:0] fifo_data_d = pipeline[31:0];
-
+       xfer_active <= 0;
+     else if(rd_eop_i & ~full)  // In case we can't store last line right away
+       xfer_active <= 0;
+     else if(rd_sop_i)
+       xfer_active <= 1;
+   
+   assign      write = xfer_active & ~full;
+   
+   assign      rd_read_o = write;
+   assign      rd_done_o = 0;        // Always take everything we're given
+   assign      rd_error_o = 0;       // No chance for errors anticipated
+   
+   
+   // FIXME Implement flow control
+   
+   reg [15:0]  second_word;
+   reg [33:0]  pipeline;
+   
+   wire        throttle_me = 0;   // Flow control here
+   
+   assign      read = (state==RUN2) | ((state==IDLE) & ~empty & ~sop_o);  
+   // 2nd half of above probably not necessary.  Just in case we get junk 
between packets
+   
    always @(posedge clk)
      if(rst)
        begin
@@ -85,35 +108,30 @@
        case(state)
         IDLE :
           begin
-             {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_COMMA,K_COMMA};
-             if(fifo_ready_d)
-               state <= START;
+             if(sop_o & ~empty & ~throttle_me)
+               begin
+                  {ser_tkmsb,ser_tklsb,ser_t} <= 
{2'b11,K_PKT_START,K_PKT_START};
+                  state <= RUN1;
+               end
+             else
+               {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_COMMA,K_COMMA};
           end
-        START :
-          begin
-             {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_START,K_PKT_START};
-             state <= RUN1;
-          end
         RUN1 :
           begin
-             {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,fifo_data_d[15:0]};
-             state <= RUN2;
-             second_word <= fifo_data_d[31:16];
+             if(empty | throttle_me)
+               {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_COMMA,K_COMMA};
+             else
+               begin
+                  {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[15:0]};
+                  state <= RUN2;
+               end
           end
         RUN2 :
           begin
-             {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,second_word};
-             if(fifo_empty_i)
+             {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[31:16]};
+             if(eop_o)
                state <= DONE;
-             else if(fifo_ready_d)
-               state <= RUN1;
              else
-               state <= WAIT;
-          end
-        WAIT :   // WAIT only necessary if the FIFO is shared and isn't always 
ready
-          begin
-             {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_COMMA,K_COMMA};
-             if(fifo_ready_d)
                state <= RUN1;
           end
         DONE :
@@ -124,25 +142,26 @@
         SENDCRC :
           begin
              {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC};
+             state <= WAIT;
+          end
+        WAIT :
+          begin
+             {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_COMMA,K_COMMA};
              state <= IDLE;
           end
         default
           state <= IDLE;
        endcase // case(state)
    
-   assign fifo_read_o = ((state == RUN1) & ~fifo_empty_i);   // FIXME This is 
the critical path
-   assign fifo_done_o = 1'b0;  // Unused -- we always send everything we're 
given
-   assign fifo_error_o = 1'b0; // Unused -- there should never be any errors
-   
    always @(posedge clk)
      if(rst)
        CRC <= 16'hFFFF;
      else if(state == IDLE)
        CRC <= 16'hFFFF;
-     else if((state==RUN1)||(state==RUN2))
+     else if( (~empty & ~throttle_me & (state==RUN1)) || (state==RUN2) )
        CRC <= nextCRC;
-
-   CRC16_D16 
crc_blk(((state==RUN1)?fifo_data_i[15:0]:second_word),CRC,nextCRC);
-
+   
+   CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, 
nextCRC);
+   
 endmodule // serdes_tx