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[Commit-gnuradio] r6440 - gnuradio/branches/developers/matt/u2f/control_
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From: |
matt |
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Subject: |
[Commit-gnuradio] r6440 - gnuradio/branches/developers/matt/u2f/control_lib |
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Date: |
Fri, 14 Sep 2007 02:31:22 -0600 (MDT) |
Author: matt
Date: 2007-09-14 02:31:21 -0600 (Fri, 14 Sep 2007)
New Revision: 6440
Added:
gnuradio/branches/developers/matt/u2f/control_lib/buffer_int_tb.v
Removed:
gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/buffer_int.v
gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
reworked buffer interface, seems to be working, more verification needed
Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_int.v
2007-09-14 03:59:49 UTC (rev 6439)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_int.v
2007-09-14 08:31:21 UTC (rev 6440)
@@ -3,7 +3,7 @@
// Read port is read-acknowledge
// FIXME do we want to be able to interleave reads and writes?
-module fifo_int
+module buffer_int
#(parameter BUFF_NUM = 0)
(// Control Interface
input clk,
@@ -25,22 +25,21 @@
input wr_write_i,
input wr_done_i,
input wr_error_i,
- output wr_ready_o,
- output wr_full_o,
+ output reg wr_ready_o,
+ output reg wr_full_o,
// Read FIFO Interface
output [31:0] rd_dat_o,
input rd_read_i,
input rd_done_i,
input rd_error_i,
- output rd_ready_o,
- output rd_empty_o
+ output reg rd_sop_o,
+ output reg rd_eop_o
);
reg [31:0] ctrl_reg;
reg go_reg;
- reg rd_empty_reg;
-
+
always @(posedge clk)
go_reg <= go;
@@ -77,13 +76,18 @@
begin
addr_o <= 0;
state <= IDLE;
- rd_empty_reg <= 1;
+ rd_sop_o <= 0;
+ rd_eop_o <= 0;
+ wr_ready_o <= 0;
+ wr_full_o <= 0;
end
else
if(clear)
begin
state <= IDLE;
- rd_empty_reg <= 1;
+ rd_sop_o <= 0;
+ rd_eop_o <= 0;
+ wr_ready_o <= 0;
end
else
case(state)
@@ -97,61 +101,71 @@
begin
addr_o <= firstline;
state <= WRITING;
+ wr_ready_o <= 1;
end
- // FIXME what if they try to read/write when we're not in that state?
PRE_READ :
begin
state <= READING;
addr_o <= addr_o + 1;
- rd_empty_reg <= 0;
+ rd_sop_o <= 1;
end
READING :
- if(rd_read_i)
+ if(rd_error_i)
+ state <= ERROR;
+ else if(rd_done_i)
+ state <= DONE;
+ else if(rd_read_i)
begin
+ rd_sop_o <= 0;
addr_o <= addr_o + 1;
- if(rd_error_i)
- begin
- state <= ERROR;
- rd_empty_reg <= 1;
- end
- else if((addr_o == lastline + 9'd1)|rd_done_i)
- begin
- state <= DONE;
- rd_empty_reg <= 1;
- end
+ if(addr_o == lastline)
+ rd_eop_o <= 1;
+ else
+ rd_eop_o <= 0;
+ if(rd_eop_o)
+ state <= DONE;
end
WRITING :
begin
if(wr_error_i)
- state <= ERROR;
+ begin
+ state <= ERROR;
+ wr_ready_o <= 0;
+ end
else
begin
if(wr_write_i)
begin
+ wr_ready_o <= 0;
addr_o <= addr_o + 1;
+ if(addr_o == (lastline-1))
+ wr_full_o <= 1;
if(addr_o == lastline)
state <= DONE;
end
if(wr_done_i)
- state <= DONE;
+ begin
+ state <= DONE;
+ wr_ready_o <= 0;
+ end
end // else: !if(wr_error_i)
end // case: WRITING
+
+ DONE :
+ begin
+ rd_eop_o <= 0;
+ rd_sop_o <= 0;
+ wr_ready_o <= 0;
+ wr_full_o <= 0;
+ end
endcase // case(state)
// FIXME ignores step for now
- //assign rd_empty_o = (state != READING); // && (state != PRE_READ);
- assign rd_empty_o = rd_empty_reg; // timing fix?
- //assign rd_ready_o = (state == READING);
- assign rd_ready_o = ~rd_empty_reg; // timing fix?
-
- assign wr_full_o = (state != WRITING);
- assign wr_ready_o = (state == WRITING);
-
assign we_o = (state == WRITING) && wr_write_i; // FIXME potential
critical path
// IF this is a timing problem, we could always write when
in this state
assign en_o = ~((state==READING)& ~rd_read_i); // FIXME potential
critical path
@@ -159,8 +173,18 @@
assign done = (state == DONE);
assign error = (state == ERROR);
+endmodule // buffer_int
+
+// Unused old code
+ //assign rd_empty_o = (state != READING); // && (state != PRE_READ);
+ //assign rd_empty_o = rd_empty_reg; // timing fix?
+ //assign rd_ready_o = (state == READING);
+ //assign rd_ready_o = ~rd_empty_reg; // timing fix?
+
//wire rd_en = (state == PRE_READ) || ((state == READING) &&
rd_read_i);
//wire wr_en = (state == WRITING) && wr_write_i; // IF this is a
timing problem, we could always enable when in this state
//assign en_o = rd_en | wr_en;
-endmodule // fifo_int
+ // assign wr_full_o = (state != WRITING);
+ // assign wr_ready_o = (state == WRITING);
+
Copied: gnuradio/branches/developers/matt/u2f/control_lib/buffer_int_tb.v (from
rev 6412, gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v)
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_int_tb.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_int_tb.v
2007-09-14 08:31:21 UTC (rev 6440)
@@ -0,0 +1,355 @@
+
+module buffer_int_tb ();
+
+ reg clk = 0;
+ reg rst = 1;
+
+ initial #100 rst = 0;
+ always #5 clk = ~clk;
+
+ wire en, we;
+ wire [8:0] addr;
+ wire [31:0] fifo2buf, buf2fifo;
+
+ wire [31:0] rd_dat_o;
+ wire rd_sop_o, rd_eop_o;
+ reg rd_done_i = 0, rd_error_i = 0, rd_read_i = 0;
+
+ reg [31:0] wr_dat_i = 0;
+ reg wr_write_i=0, wr_done_i = 0, wr_error_i = 0;
+ wire wr_ready_o, wr_full_o;
+
+ reg clear = 0, write = 0, read = 0;
+ reg [8:0] firstline = 0, lastline = 0;
+ wire [3:0] step = 1;
+ wire [31:0] ctrl_word =
{4'b0,3'b0,clear,write,read,step,lastline,firstline};
+ reg go = 0;
+ wire done, error;
+
+ buffer_int buffer_int
+ (.clk(clk),.rst(rst),
+ .ctrl_word(ctrl_word),.go(go),
+ .done(done),.error(error),
+
+ // Buffer Interface
+ .en_o(en),.we_o(we),.addr_o(addr),
+ .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
+
+ // Write FIFO Interface
+ .wr_dat_i(wr_dat_i), .wr_write_i(wr_write_i), .wr_done_i(wr_done_i),
.wr_error_i(wr_error_i),
+ .wr_ready_o(wr_ready_o), .wr_full_o(wr_full_o),
+
+ // Read FIFO Interface
+ .rd_dat_o(rd_dat_o), .rd_read_i(rd_read_i), .rd_done_i(rd_done_i),
.rd_error_i(rd_error_i),
+ .rd_sop_o(rd_sop_o), .rd_eop_o(rd_eop_o)
+ );
+
+ reg ram_en = 0, ram_we = 0;
+ reg [8:0] ram_addr = 0;
+ reg [31:0] ram_data = 0;
+
+ ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port
+ (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr),
.dia(ram_data), .doa(),
+ .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf),
.dob(buf2fifo) );
+
+ initial
+ begin
+ @(negedge rst);
+ @(posedge clk);
+ FillRAM;
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing full read, no wait states.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(6,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing full read, 2 wait states.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(6,2);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing full read, done ON the last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(5,2);
+ rd_done_i <= 1;
+ ReadALine;
+ rd_done_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 0 wait states, then nothing after
last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(3,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 0 wait states, then done after last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(3,0);
+ rd_done_i <= 1;
+ @(posedge clk);
+ rd_done_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 0 wait states, then done at same time
as last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(2,0);
+ rd_done_i <= 1;
+ ReadALine;
+ rd_done_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 3 wait states, then error at same time
as last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(2,3);
+ rd_error_i <= 1;
+ ReadALine;
+ rd_error_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing Reading too much, 3 wait states.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(9,3);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(500,511);
+ $display("Testing full read, to the end of the buffer.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(12,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(505,3);
+ $display("Testing full read, wraparound");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(11,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(10,15);
+ $display("Testing Full Write, no wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,72);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(18,23);
+ $display("Testing Full Write, 1 wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,101);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(27,40);
+ $display("Testing Partial Write, 0 wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,201);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(35,200);
+ $display("Testing Partial Write, 0 wait states, then done");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,301);
+ wr_done_i <= 1;
+ @(posedge clk);
+ wr_done_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(45,200);
+ $display("Testing Partial Write, 0 wait states, then done and write");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,301);
+ wr_done_i <= 1;
+ WriteALine(400);
+ wr_done_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(0,52);
+ $display("Testing read after write");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(53,0);
+ repeat (10)
+ @(posedge clk);
+
+
+ ResetBuffer;
+ repeat(100)
+ @(posedge clk);
+ $finish;
+ end
+
+ always @(posedge clk)
+ if(rd_read_i == 1'd1)
+ $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_dat_o,
rd_sop_o, rd_eop_o);
+
+ always @(posedge clk)
+ if(wr_write_i == 1'd1)
+ $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_dat_i,
wr_ready_o, wr_full_o);
+
+ initial begin
+ $dumpfile("buffer_int_tb.vcd");
+ $dumpvars(0,buffer_int_tb);
+ end
+
+ task FillRAM;
+ begin
+ ram_addr <= 0;
+ ram_data <= 0;
+ @(posedge clk);
+ ram_en <= 1;
+ ram_we <= 1;
+ @(posedge clk);
+ repeat (511)
+ begin
+ ram_addr <= ram_addr + 1;
+ ram_data <= ram_data + 1;
+ ram_en <= 1;
+ ram_we <= 1;
+ @(posedge clk);
+ end
+ ram_en <= 0;
+ ram_we <= 0;
+ @(posedge clk);
+ $display("Filled the RAM");
+ end
+ endtask // FillRAM
+
+ task ResetBuffer;
+ begin
+ clear <= 1; read <= 0; write <= 0;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Reset");
+ end
+ endtask // ClearBuffer
+
+ task SetBufferWrite;
+ input [8:0] start;
+ input [8:0] stop;
+ begin
+ clear <= 0; read <= 0; write <= 1;
+ firstline <= start;
+ lastline <= stop;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Set for Write");
+ end
+ endtask // SetBufferWrite
+
+ task SetBufferRead;
+ input [8:0] start;
+ input [8:0] stop;
+ begin
+ clear <= 0; read <= 1; write <= 0;
+ firstline <= start;
+ lastline <= stop;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Set for Read");
+ end
+ endtask // SetBufferRead
+
+ task ReadALine;
+ begin
+ #1 rd_read_i <= 1;
+ @(posedge clk);
+ rd_read_i <= 0;
+ end
+ endtask // ReadALine
+
+ task ReadLines;
+ input [9:0] lines;
+ input [7:0] wait_states;
+ begin
+ $display("Read Lines: Number %d, Wait States %d",lines,wait_states);
+ repeat (lines)
+ begin
+ ReadALine;
+ repeat (wait_states)
+ @(posedge clk);
+ end
+ end
+ endtask // ReadLines
+
+ task WriteALine;
+ input [31:0] value;
+ begin
+ #1 wr_write_i <= 1;
+ wr_dat_i <= value;
+ @(posedge clk);
+ wr_write_i <= 0;
+ end
+ endtask // WriteALine
+
+ task WriteLines;
+ input [9:0] lines;
+ input [7:0] wait_states;
+ input [31:0] value;
+ begin
+ $display("Write Lines: Number %d, Wait States %d",lines,wait_states);
+ repeat(lines)
+ begin
+ value <= value + 1;
+ WriteALine(value);
+ repeat(wait_states)
+ @(posedge clk);
+ end
+ end
+ endtask // WriteLines
+
+endmodule // buffer_int_tb
Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-09-14 03:59:49 UTC (rev 6439)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-09-14 08:31:21 UTC (rev 6440)
@@ -138,7 +138,7 @@
.addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
.clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),
.addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i]));
- fifo_int #(.BUFF_NUM(i)) fifo_int
+ buffer_int #(.BUFF_NUM(i)) fifo_int
(.clk(stream_clk),.rst(stream_rst),
.ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),
.done(done[i]),.error(error[i]),
Deleted: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int_tb.v
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