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[Commit-gnuradio] r5848 - gnuradio/branches/developers/matt/u2f/control_
From: |
matt |
Subject: |
[Commit-gnuradio] r5848 - gnuradio/branches/developers/matt/u2f/control_lib |
Date: |
Tue, 26 Jun 2007 15:51:12 -0600 (MDT) |
Author: matt
Date: 2007-06-26 15:51:12 -0600 (Tue, 26 Jun 2007)
New Revision: 5848
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
Log:
believed to be completely working serdes for even and odd situations, need to
test crc fails and too-long packets
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
2007-06-26 21:42:55 UTC (rev 5847)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
2007-06-26 21:51:12 UTC (rev 5848)
@@ -46,39 +46,53 @@
localparam K_ERROR = 8'b000_00000; // 0x00 K00.0
localparam IDLE = 3'd0;
- localparam EVEN = 3'd1;
- localparam ODD = 3'd2;
- localparam CRC_EVEN = 3'd3;
- localparam CRC_ODD = 3'd4;
- localparam ERROR = 3'd5;
- localparam DONE = 3'd6;
+ localparam PKT = 3'd1;
+ localparam CRC_CHECK = 3'd2;
+ localparam ERROR = 3'd3;
+ localparam DONE = 3'd4;
- wire [17:0] rxd;
+ wire [17:0] even_data;
+ reg [17:0] odd_data;
+ wire [17:0] chosen_data;
+ reg odd;
+
reg [31:0] line;
- reg [15:0] halfline;
- reg data_valid, phase;
- reg [7:0] holder;
+ reg [15:0] halfline;
+ reg data_valid, phase;
+ reg [8:0] holder;
+
+ reg [2:0] state;
- wire crc_pass;
-
- reg [2:0] state;
-
-
ss_rcvr #(.WIDTH(18)) ss_rcvr
(.rxclk(ser_rx_clk),.sysclk(clk),.rst(rst),
- .data_in({ser_rkmsb,ser_rklsb,ser_r}),.data_out(rxd),
+ .data_in({ser_rkmsb,ser_rklsb,ser_r}),.data_out(even_data),
.clock_present());
always @(posedge clk)
+ if(rst)
+ holder <= 9'd0;
+ else
+ holder <= {even_data[17],even_data[15:8]};
+
+ always @(posedge clk)
+ if(rst)
+ odd_data <= 18'd0;
+ else
+ odd_data <= {even_data[16],holder[8],even_data[7:0],holder[7:0]};
+
+ assign chosen_data = odd ? odd_data : even_data;
+
+ always @(posedge clk)
if(phase == 1)
- line = {rxd[15:0], halfline};
-
+ line = {chosen_data[15:0], halfline};
+
always @(posedge clk)
if(rst)
begin
state <= IDLE;
data_valid <= 0;
phase <= 0;
+ odd <= 0;
end
else
case(state)
@@ -86,66 +100,54 @@
begin
data_valid <= 0;
phase <= 0;
- if(rxd == {2'b11,K_PKT_START,K_PKT_START})
- state <= EVEN;
- else if((rxd[17:16]==2'b01) && (rxd[7:0]==K_PKT_START))
+ if(even_data == {2'b11,K_PKT_START,K_PKT_START})
begin
- state <= ODD;
- holder <= rxd[15:8];
+ state <= PKT;
+ odd <= 0;
end
+ else if(odd_data == {2'b11,K_PKT_START,K_PKT_START})
+ begin
+ state <= PKT;
+ odd <= 1;
+ end
end
- EVEN :
- case(rxd[17:16])
- 2'b00 :
- begin
- data_valid <= 1;
- phase <= ~phase;
- halfline <= rxd[15:0];
- end
- 2'b11 :
- if((rxd[15:0] == {K_PKT_END,K_PKT_END}) & ~phase)
- begin
- state <= CRC_EVEN;
- data_valid <= 0;
- end
- else
- begin
- data_valid <= 0;
- state <= ERROR;
- end
- default :
+
+ PKT :
+ if(chosen_data == {2'b11,K_PKT_END,K_PKT_END})
+ if(~phase)
begin
+ state <= CRC_CHECK;
data_valid <= 0;
+ end
+ else
+ begin
state <= ERROR;
+ data_valid <= 0;
end
- endcase // case(rxd[17:16])
- ODD :
- if(~rxd[16])
- begin
+ else if(chosen_data[17:16] == 2'b00)
+ begin
data_valid <= 1;
phase <= ~phase;
- holder <= rxd[15:8];
- halfline <= {rxd[7:0],holder};
- if(rxd[17:16]==2'b10)
- state <= CRC_ODD;
- else
- state <= ERROR;
+ halfline <= chosen_data[15:0];
end
else
- state <= ERROR;
- CRC_EVEN :
- if(rxd[15:0] == CRC)
+ begin
+ data_valid <= 0;
+ state <= ERROR;
+ end // else: !if(chosen_data[17:16] == 2'b00)
+
+ CRC_CHECK :
+ if(chosen_data[15:0] == CRC)
state <= DONE;
else
state <= ERROR;
- CRC_ODD :
- state <= IDLE;
+
ERROR :
state <= IDLE;
DONE :
state <= IDLE;
endcase // case(state)
-
+
reg [15:0] CRC;
wire [15:0] nextCRC;
@@ -158,7 +160,6 @@
CRC <= nextCRC;
CRC16_D16 crc_blk(halfline,CRC,nextCRC);
- assign crc_pass = ~|nextCRC;
assign fifo_data_o = line;
assign fifo_write_o = data_valid & ~phase;
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
2007-06-26 21:42:55 UTC (rev 5847)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
2007-06-26 21:51:12 UTC (rev 5848)
@@ -4,8 +4,8 @@
reg clk, rst;
wire ser_rx_clk, ser_tx_clk;
- wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb;
- wire [15:0] ser_r, ser_t;
+ wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb, ser_rklsb_odd,
ser_rkmsb_odd;
+ wire [15:0] ser_r, ser_t, ser_r_odd;
initial clk = 0;
initial rst = 1;
@@ -92,10 +92,22 @@
);
// Simulate the connection
- assign ser_rx_clk = ser_tx_clk;
- assign ser_rkmsb = ser_tkmsb;
- assign ser_rklsb = ser_tklsb;
- assign ser_r = ser_t;
+ assign ser_rx_clk = ser_tx_clk;
+
+ reg even = 0;
+
+ reg hold_k;
+ reg [7:0] hold_dat;
+
+ always @(posedge clk) hold_k <= ser_tklsb;
+ always @(posedge clk) hold_dat <= ser_t[15:8];
+ assign ser_rklsb_odd = hold_k;
+ assign ser_rkmsb_odd = ser_tklsb;
+ assign ser_r_odd = {ser_t[7:0], hold_dat};
+
+ assign ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd;
+ assign ser_rklsb = even ? ser_tklsb : ser_rklsb_odd;
+ assign ser_r = even ? ser_t : ser_r_odd;
// Fill the ram
initial wb_en_rx <= 0;
@@ -132,8 +144,27 @@
$display("Send read_go");
@(posedge clk);
read_go_tx = 0;
-
-
+ @(posedge clk);
+ @(posedge fdone_rx);
+ @(posedge clk);
+ @(posedge clk);
+ $display("Done with packet 1 (odd), send another");
+ even <= 1;
+ @(posedge clk);
+ @(posedge clk);
+ write_go_rx <= 1;
+ @(posedge clk);
+ write_go_rx <= 0;
+ @(posedge clk);
+ read_go_tx <= 1;
+ @(posedge clk);
+ read_go_tx <= 0;
+ @(posedge clk);
+ @(posedge fdone_rx);
+ $display("Got second packet (even)");
+ repeat(10)
+ @(posedge clk);
+ $finish;
end // initial begin
initial begin
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