[Commit-gnuradio] r5260 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-05-08 21:36:42 -0600 (Tue, 08 May 2007)
New Revision: 5260

Added:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_2k.v
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
   gnuradio/branches/developers/matt/u2f/control_lib/decoder_3_8.v
   gnuradio/branches/developers/matt/u2f/control_lib/serdes.v
   gnuradio/branches/developers/matt/u2f/control_lib/wb_regfile_2clock.v
Log:
first cut at buffer pool for serdes, gigE, and DSP use


Added: gnuradio/branches/developers/matt/u2f/control_lib/buffer_2k.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_2k.v               
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_2k.v       
2007-05-09 03:36:42 UTC (rev 5260)
@@ -0,0 +1,37 @@
+
+
+module buffer_2k
+  (input clka,
+   input ena,
+   input wea,
+   input [8:0] addra,
+   input [31:0] dia,
+   output [31:0] doa,
+
+   input clkb,
+   input enb,
+   input web,
+   input [8:0] addrb,
+   input [31:0] dib,
+   output [31:0] dob);
+   
+   reg [31:0]   ram [511:0];
+   reg [31:0]   doa,dob;
+
+   always @(posedge clka) begin
+      if (ena)
+        begin
+           if (wea)
+             ram[addra] <= dia;
+           doa <= ram[addra];
+        end
+   end
+   always @(posedge clkb) begin
+      if (enb)
+        begin
+           if (web)
+             ram[addrb] <= dib;
+           dob <= ram[addrb];
+        end
+   end
+endmodule // buffer_2k

Added: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v             
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-05-09 03:36:42 UTC (rev 5260)
@@ -0,0 +1,118 @@
+
+// Buffer pool.  Contains 8 buffers, each 2K (512 by 32).  Each buffer
+// is a dual-ported RAM.  Port A on each of them is indirectly connected 
+// to the wishbone bus by a bridge.  Port B may be connected any one of the
+// 6 FIFO-like streaming interaces, or disconnected.  The wishbone bus
+// provides access to all 8 buffers, and also controls the connections
+// between the ports and the buffers, allocating them as needed.
+
+// wb_adr is 13 bits -- 
+//  bit 12 control (1) or data (1)
+//  bits 11:9 select which buffer
+
+module buffer_pool
+  (input wb_clk_i,
+   input wb_rst_i,
+   input wb_we_i,
+   input wb_stb_i,
+   input [12:0] wb_adr_i,
+   input [31:0] wb_dat_i,   
+   output reg [31:0] wb_dat_o,
+   output reg wb_ack_o,
+   output wb_err_o,
+
+   input stream_clk,
+   // Write Interfaces
+   input [31:0] din_0,
+   input write_0,
+   input done_0,
+   output wr_rdy_0,
+   
+   input [31:0] din_1,
+   input write_1,
+   input done_1,
+   output wr_rdy_1,
+   
+   input [31:0] din_2,
+   input write_2,
+   input done_2,
+   output wr_rdy_2,
+
+   // Read Interfaces
+   output [31:0] dout_0,
+   output rd_rdy_0,
+   input read_0,
+   
+   output [31:0] dout_1,
+   output rd_rdy_1,
+   input read_1,
+   
+   output [31:0] dout_2,
+   output rd_rdy_2,
+   input read_2    
+   );
+
+   assign wb_err_o = 1'b0;  // Unused for now
+   
+   wire [7:0] sel_a;
+   wire [31:0] buf0_outa, buf1_outa, buf2_outa, buf3_outa, buf4_outa, 
buf5_outa, buf6_outa, buf7_outa;
+   
+   decoder_3_8 dec(.sel(wb_adr_i[11:9]),.res(sel_a));
+      
+   buffer_2k buf_0
+     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[0]),.wea(wb_we_i),
+      .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf0_outa),
+      .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+    
+   buffer_2k buf_1
+     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[1]),.wea(wb_we_i),
+      .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf1_outa),
+      .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+   
+   buffer_2k buf_2
+     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[2]),.wea(wb_we_i),
+      .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf2_outa),
+      .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+   
+   buffer_2k buf_3
+     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[3]),.wea(wb_we_i),
+      .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf3_outa),
+      .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+   
+   buffer_2k buf_4
+     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[4]),.wea(wb_we_i),
+      .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf4_outa),
+      .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+   
+   buffer_2k buf_5
+     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[5]),.wea(wb_we_i),
+      .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf5_outa),
+      .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+   
+   buffer_2k buf_6
+     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[6]),.wea(wb_we_i),
+      .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf6_outa),
+      .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+   
+   buffer_2k buf_7
+     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[7]),.wea(wb_we_i),
+      .addra(wb_adr_i[8:0]),.dia(wb_dat_i),.doa(buf7_outa),
+      .clkb(stream_clk),.enb(),.web(),.addrb(),.dib(),.dob());
+   
+  always @(posedge wb_clk_i)
+     if(wb_stb_i)
+       case(wb_adr_i)
+        3'd0 : wb_dat_o <= buf0_outa;
+        3'd1 : wb_dat_o <= buf1_outa;
+        3'd2 : wb_dat_o <= buf2_outa;
+        3'd3 : wb_dat_o <= buf3_outa;
+        3'd4 : wb_dat_o <= buf4_outa;
+        3'd5 : wb_dat_o <= buf5_outa;
+        3'd6 : wb_dat_o <= buf6_outa;
+        3'd7 : wb_dat_o <= buf7_outa;
+       endcase // case(wb_adr_i)
+   
+   always @(posedge wb_clk_i)
+     wb_ack_o <= wb_stb_i;
+   
+endmodule // buffer_pool

Added: gnuradio/branches/developers/matt/u2f/control_lib/decoder_3_8.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/decoder_3_8.v             
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/decoder_3_8.v     
2007-05-09 03:36:42 UTC (rev 5260)
@@ -0,0 +1,21 @@
+
+module decoder_3_8 
+  (input [2:0] sel, 
+   output reg [7:0] res);
+
+   always @(sel or res)
+     begin
+        case (sel)
+          3'b000 : res = 8'b00000001;
+          3'b001 : res = 8'b00000010;
+          3'b010 : res = 8'b00000100;
+          3'b011 : res = 8'b00001000;
+          3'b100 : res = 8'b00010000;
+          3'b101 : res = 8'b00100000;
+          3'b110 : res = 8'b01000000;
+          default : res = 8'b10000000;
+        endcase // case(sel)
+     end // always @ (sel or res)
+
+endmodule // decoder_3_8
+

Added: gnuradio/branches/developers/matt/u2f/control_lib/serdes.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes.v                  
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes.v  2007-05-09 
03:36:42 UTC (rev 5260)
@@ -0,0 +1,39 @@
+
+module serdes
+  (input clk,
+   input rst,
+
+   // TX HW Interface
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   // RX HW Interface
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+
+   // TX Stream Interface
+   input [31:0] dout_0,
+   input rd_rdy_0,
+   output read_0,
+
+   // RX Stream Interface
+   output [31:0] din_0,
+   output write_0,
+   output done_0,
+   input wr_rdy_0,
+
+   // HW controls -- FIXME -- maybe these should be controlled by the 
processor directly.
+   
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en
+   );
+      
+   
+
+endmodule // serdes

Added: gnuradio/branches/developers/matt/u2f/control_lib/wb_regfile_2clock.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_regfile_2clock.v       
                        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_regfile_2clock.v       
2007-05-09 03:36:42 UTC (rev 5260)
@@ -0,0 +1,107 @@
+
+module wb_regfile_2clock
+  (input wb_clk_i,
+   input wb_rst_i,
+   input wb_stb_i,
+   input wb_we_i,
+   input [15:0] wb_adr_i,
+   input [3:0] wb_sel_i,
+   input [31:0] wb_dat_i,
+   output [31:0] wb_dat_o,
+   output wb_ack_o,
+   input alt_clk,
+   input alt_rst,
+   
+   output reg [31:0] reg00,
+   output reg [31:0] reg01,
+   output reg [31:0] reg02,
+   output reg [31:0] reg03,
+   output reg [31:0] reg04,
+   output reg [31:0] reg05,
+   output reg [31:0] reg06,
+   output reg [31:0] reg07
+   );
+
+   reg [15:0]   addr_reg;
+   reg [3:0]    sel_reg;
+   reg [31:0]   dat_reg;
+   reg                  wr_ret1, wr_ret2, we_reg, stb_reg;
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       begin
+         addr_reg <= 0;
+         sel_reg <= 0;
+         dat_reg <= 0;
+       end
+     else if(wb_stb_i & wb_we_i)
+       begin
+         addr_reg <= wb_adr_i;
+         sel_reg <= wb_sel_i;
+         dat_reg <= wb_dat_i;
+       end
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       {we_reg,stb_reg} <= 2'b0;
+     else
+       {we_reg,stb_reg} <= {wb_we_i,wb_stb_i};
+
+   assign wb_ack_o = stb_reg;
+   
+   always @(posedge alt_clk)
+     if(alt_rst)
+       {wr_ret2, wr_ret1} <= 2'b0;
+     else
+       {wr_ret2, wr_ret1} <= {wr_ret1, we_reg & stb_reg};
+   
+   always @(posedge alt_clk)
+     if(alt_rst)
+       begin
+         reg00 <= 0;
+         reg01 <= 0;
+         reg02 <= 0;
+         reg03 <= 0;
+         reg04 <= 0;
+         reg05 <= 0;
+         reg06 <= 0;
+         reg07 <= 0;
+       end // if (alt_rst)
+     else if(wr_ret2)
+       case(addr_reg[4:2])
+        3'd0: reg00 <= { {sel_reg[3] ? dat_reg[31:24] : reg00[31:24]},
+                         {sel_reg[2] ? dat_reg[23:16] : reg00[23:16]},
+                         {sel_reg[1] ? dat_reg[15:8] : reg00[15:8]},
+                         {sel_reg[0] ? dat_reg[7:0] : reg00[7:0]}};
+        3'd1: reg01 <= { {sel_reg[3] ? dat_reg[31:24] : reg01[31:24]},
+                         {sel_reg[2] ? dat_reg[23:16] : reg01[23:16]},
+                         {sel_reg[1] ? dat_reg[15:8] : reg01[15:8]},
+                         {sel_reg[0] ? dat_reg[7:0] : reg01[7:0]}};
+        3'd2: reg02 <= { {sel_reg[3] ? dat_reg[31:24] : reg02[31:24]},
+                         {sel_reg[2] ? dat_reg[23:16] : reg02[23:16]},
+                         {sel_reg[1] ? dat_reg[15:8] : reg02[15:8]},
+                         {sel_reg[0] ? dat_reg[7:0] : reg02[7:0]}};
+        3'd3: reg03 <= { {sel_reg[3] ? dat_reg[31:24] : reg03[31:24]},
+                         {sel_reg[2] ? dat_reg[23:16] : reg03[23:16]},
+                         {sel_reg[1] ? dat_reg[15:8] : reg03[15:8]},
+                         {sel_reg[0] ? dat_reg[7:0] : reg03[7:0]}};
+        3'd4: reg04 <= { {sel_reg[3] ? dat_reg[31:24] : reg04[31:24]},
+                         {sel_reg[2] ? dat_reg[23:16] : reg04[23:16]},
+                         {sel_reg[1] ? dat_reg[15:8] : reg04[15:8]},
+                         {sel_reg[0] ? dat_reg[7:0] : reg04[7:0]}};
+        3'd5: reg05 <= { {sel_reg[3] ? dat_reg[31:24] : reg05[31:24]},
+                         {sel_reg[2] ? dat_reg[23:16] : reg05[23:16]},
+                         {sel_reg[1] ? dat_reg[15:8] : reg05[15:8]},
+                         {sel_reg[0] ? dat_reg[7:0] : reg05[7:0]}};
+        3'd6: reg06 <= { {sel_reg[3] ? dat_reg[31:24] : reg06[31:24]},
+                         {sel_reg[2] ? dat_reg[23:16] : reg06[23:16]},
+                         {sel_reg[1] ? dat_reg[15:8] : reg06[15:8]},
+                         {sel_reg[0] ? dat_reg[7:0] : reg06[7:0]}};
+        3'd7: reg07 <= { {sel_reg[3] ? dat_reg[31:24] : reg07[31:24]},
+                         {sel_reg[2] ? dat_reg[23:16] : reg07[23:16]},
+                         {sel_reg[1] ? dat_reg[15:8] : reg07[15:8]},
+                         {sel_reg[0] ? dat_reg[7:0] : reg07[7:0]}};
+       endcase // case(addr_reg[2:0])
+   
+endmodule // wb_regfile_2clock
+