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[Commit-gnuradio] r5259 - gnuradio/branches/developers/matt/u2f/control_
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5259 - gnuradio/branches/developers/matt/u2f/control_lib |
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Date: |
Tue, 8 May 2007 21:35:56 -0600 (MDT) |
Author: matt
Date: 2007-05-08 21:35:56 -0600 (Tue, 08 May 2007)
New Revision: 5259
Added:
gnuradio/branches/developers/matt/u2f/control_lib/wb_1master.v
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
gnuradio/branches/developers/matt/u2f/control_lib/ram_wb_harvard.v
gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
Log:
reorganized -- ram loader now loads ram through the I-port, not wb
Modified: gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
2007-05-09 03:32:54 UTC (rev 5258)
+++ gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
2007-05-09 03:35:56 UTC (rev 5259)
@@ -2,7 +2,7 @@
// Adapted from VHDL code in spi_boot by Arnim Legauer
// Added a full wishbone master interface (32-bit)
-module ram_loader #(parameter AWIDTH=12)
+module ram_loader #(parameter AWIDTH=16)
(input clk_i, input rst_i,
// CPLD Interface
input cfg_clk_i, input cfg_data_i,
@@ -163,7 +163,7 @@
FSM2_INC_ADDR1:
fsm_s <= FSM2_INC_ADDR2;
FSM2_INC_ADDR2:
- if(&addr_q)
+ if(addr_q == 4095)
begin
fsm_s <= FSM2_FINISHED;
done_s <= 1'b1;
@@ -190,7 +190,7 @@
assign ram_we = ram_we_q;
assign ram_loader_done_o = (fsm_q == FSM2_FINISHED);
- // wishbone master, only writes. May be somewhat superfluous...
+ // wishbone master, only writes
reg [7:0] dat_holder;
assign wb_dat_o = {4{dat_holder}};
assign wb_stb_o = wb_we_o;
Modified: gnuradio/branches/developers/matt/u2f/control_lib/ram_wb_harvard.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/ram_wb_harvard.v
2007-05-09 03:32:54 UTC (rev 5258)
+++ gnuradio/branches/developers/matt/u2f/control_lib/ram_wb_harvard.v
2007-05-09 03:35:56 UTC (rev 5259)
@@ -2,24 +2,29 @@
// Dual ported RAM for Harvard architecture processors
// Does no forwarding
// Addresses are byte-oriented, so botton 2 address bits are ignored. FIXME
-// AWIDTH of 12 give 4K bytes
+// AWIDTH of 13 gives 8K bytes. For Spartan 3, if the total RAM size is
not a
+// multiple of 8K then BRAM space is wasted
-module ram_wb_harvard #(parameter AWIDTH=12)
- (input wb_clk_i,
- input wb_rst_i,
- input [AWIDTH-1:0] iwb_adr_i,
- output reg [31:0] iwb_dat_o,
- input iwb_stb_i,
- output reg iwb_ack_o,
-
- input [AWIDTH-1:0] dwb_adr_i,
- input [31:0] dwb_dat_i,
- output reg [31:0] dwb_dat_o,
- input dwb_we_i,
- output reg dwb_ack_o,
- input dwb_stb_i,
- input [3:0] dwb_sel_i);
+module ram_wb_harvard #(parameter AWIDTH=13)
+ (input wb_clk_i,
+ input wb_rst_i,
+ input [AWIDTH-1:0] iwb_adr_i,
+ input [31:0] iwb_dat_i,
+ output reg [31:0] iwb_dat_o,
+ input iwb_we_i,
+ output reg iwb_ack_o,
+ input iwb_stb_i,
+ input [3:0] iwb_sel_i,
+
+ input [AWIDTH-1:0] dwb_adr_i,
+ input [31:0] dwb_dat_i,
+ output reg [31:0] dwb_dat_o,
+ input dwb_we_i,
+ output reg dwb_ack_o,
+ input dwb_stb_i,
+ input [3:0] dwb_sel_i);
+
reg [7:0] ram0 [0:(1<<(AWIDTH-2))-1];
reg [7:0] ram1 [0:(1<<(AWIDTH-2))-1];
reg [7:0] ram2 [0:(1<<(AWIDTH-2))-1];
@@ -27,10 +32,7 @@
// Instruction Read Port
always @(posedge wb_clk_i)
- if(wb_rst_i)
- iwb_ack_o <= 1'b0;
- else
- iwb_ack_o <= iwb_stb_i;
+ iwb_ack_o <= iwb_stb_i;
always @(posedge wb_clk_i)
iwb_dat_o[31:24] <= ram3[iwb_adr_i[AWIDTH-1:2]];
@@ -41,12 +43,22 @@
always @(posedge wb_clk_i)
iwb_dat_o[7:0] <= ram0[iwb_adr_i[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if(iwb_we_i & iwb_stb_i & iwb_sel_i[3])
+ ram3[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[31:24];
+ always @(posedge wb_clk_i)
+ if(iwb_we_i & iwb_stb_i & iwb_sel_i[2])
+ ram2[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[23:16];
+ always @(posedge wb_clk_i)
+ if(iwb_we_i & iwb_stb_i & iwb_sel_i[1])
+ ram1[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[15:8];
+ always @(posedge wb_clk_i)
+ if(iwb_we_i & iwb_stb_i & iwb_sel_i[0])
+ ram0[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[7:0];
+
// Data Port
always @(posedge wb_clk_i)
- if(wb_rst_i)
- dwb_ack_o <= 1'b0;
- else
- dwb_ack_o <= dwb_stb_i;
+ dwb_ack_o <= dwb_stb_i;
always @(posedge wb_clk_i)
dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
Modified: gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
2007-05-09 03:32:54 UTC (rev 5258)
+++ gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
2007-05-09 03:35:56 UTC (rev 5259)
@@ -1,140 +1,47 @@
-// This module is a WB master. It sets up the clocks
-// and resets based on the power-on reset
-
-// DSP clock is the main system clock, at 100 MHz
-// It would be nice if WB_CLK could be 100 MHz, but it may
-// have to run at 1/2 rate (50 MHz) for cycle time reasons
-//
// System bootup order:
// 0 - Internal POR to reset this block. Maybe control it from CPLD in the
future?
-// 1 - Everything in reset, wb_clk from aux_clk
-// 2 - Take RAM Loader and wishbone out of reset
-// 3 - When RAM Loader done, take processor out of reset
-// 4 - When processor signals that it has set up the AD9510 properly,
-// cut over to the wb_clk derived from (1/2 speed) main fpga
clock
-// 5 - Optionally, somehow tell the CPLD to turn off the AUX clock
-//
-// FIXME Do we want to gate the DSP clock?
+// 1 - Everything in reset
+// 2 - Take RAM Loader out of reset
+// 3 - When RAM Loader done, take processor and wishbone out of reset
module system_control
- (
- // Input Clocks
- input aux_clk_i,
- input clk_fpga_i,
-
- //Input Resets
- // None for now, maybe take POR from CPLD later
-
- // Output clocks
- output dsp_clk_o,
- output wb_clk_o,
-
- // Output Resets
- output ram_loader_rst_o,
- output reg processor_rst_o,
+ (input wb_clk_i,
+ output reg ram_loader_rst_o,
output reg wb_rst_o,
- output reg dsp_rst_o,
-
- // Control inputs
- input ram_loader_done_i,
- input clock_ready_i,
-
- // Debug outputs
- output [7:0] debug_o
+ input ram_loader_done_i
);
- reg POR;
+ reg POR = 1'b1;
reg [3:0] POR_ctr;
- initial POR = 1'b0;
- initial #1 POR = 1'b1;
+
initial POR_ctr = 4'd0;
- always @(posedge aux_clk_i)
+ always @(posedge wb_clk_i)
if(POR_ctr == 4'd15)
POR <= 1'b0;
else
POR_ctr <= POR_ctr + 4'd1;
- reg start, started, finished;
+ always @(posedge POR or posedge wb_clk_i)
+ if(POR)
+ ram_loader_rst_o <= 1'b1;
+ else
+ ram_loader_rst_o <= #1 1'b0;
- // Control the resets and start the initial programming of the clocks
- always @(posedge POR or posedge aux_clk_i)
+ // Main system reset
+ reg delayed_rst;
+
+ always @(posedge POR or posedge wb_clk_i)
if(POR)
begin
wb_rst_o <= 1'b1;
- finished <= #1 1'b0;
- start <= #1 1'b0;
- started <= #1 1'b0;
+ delayed_rst <= 1'b1;
end
- else if(wb_rst_o)
- wb_rst_o <= #1 1'b0;
- else if(start)
- start <= #1 1'b0;
- else if(!started)
+ else if(ram_loader_done_i)
begin
- started <= #1 1'b1;
- start <= #1 1'b1;
+ delayed_rst <= 1'b0;
+ wb_rst_o <= delayed_rst;
end
- else if(clock_ready_i)
- finished <= #1 1'b1;
- assign ram_loader_rst_o = wb_rst_o;
-
- // Processor Reset
- always @(posedge POR or posedge wb_clk_o)
- if(POR)
- processor_rst_o <= 1'b1;
- else if(ram_loader_done_i)
- processor_rst_o <= 1'b0;
-
- reg gate_dsp_clk;
- // DSP Reset
- always @(posedge POR or posedge dsp_clk_o)
- if(POR)
- dsp_rst_o <= 1'b1;
- else
- dsp_rst_o <= ~gate_dsp_clk;
-
- ////////////////////////////////////////////////////////////
- // Control the clocks
- reg fin_ret_half, fin_ret_aux; // Retimed finish signals
-
- // Generate dsp_clk
- reg clock_ready_ret, half_clk;
- always @(posedge clk_fpga_i or posedge POR)
- if(POR)
- clock_ready_ret <= 1'b0;
- else
- clock_ready_ret <= clock_ready_i;
-
- always @(negedge clk_fpga_i or posedge POR)
- if(POR)
- gate_dsp_clk <= 1'b0;
- else
- gate_dsp_clk <= clock_ready_ret;
-
- assign dsp_clk_o = gate_dsp_clk & clk_fpga_i;
-
- // Generate half frequency clock
- always @(posedge POR or posedge clk_fpga_i)
- if(POR)
- half_clk <= 1'b0;
- else
- half_clk <= ~half_clk;
-
- always @(posedge POR or negedge half_clk)
- if(POR)
- fin_ret_half <= #1 1'b0;
- else
- fin_ret_half <= #1 fin_ret_aux;
-
- always @(posedge POR or negedge aux_clk_i)
- if(POR)
- fin_ret_aux <= #1 1'b0;
- else
- fin_ret_aux <= #1 finished;
-
- assign wb_clk_o = (half_clk & fin_ret_half) | (aux_clk_i & ~fin_ret_aux);
-
endmodule // system_control
Added: gnuradio/branches/developers/matt/u2f/control_lib/wb_1master.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_1master.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_1master.v
2007-05-09 03:35:56 UTC (rev 5259)
@@ -0,0 +1,258 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// WISHBONE Connection Bus Top Level ////
+//// ////
+//// ////
+//// Original Author: Johny Chi ////
+//// address@hidden ////
+//// Modified By Matt Ettus, address@hidden ////
+//// ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// Up to 8 slaves share a Wishbone Bus connection to 1 master
+
+ module wb_1master
+ #(parameter s0_addr_w = 4, // slave 0 address
decode width
+ parameter s0_addr = 4'h0, // slave 0 address
+ parameter s1_addr_w = 4 , // slave 1 address
decode width
+ parameter s1_addr = 4'h1, // slave 1 address
+ parameter s27_addr_w = 8 , // slave 2 to slave 7
address decode width
+ parameter s2_addr = 8'h92, // slave 2 address
+ parameter s3_addr = 8'h93, // slave 3 address
+ parameter s4_addr = 8'h94, // slave 4 address
+ parameter s5_addr = 8'h95, // slave 5 address
+ parameter s6_addr = 8'h96, // slave 6 address
+ parameter s7_addr = 8'h97, // slave 7 address
+
+ parameter dw = 32, // Data bus Width
+ parameter aw = 32, // Address bus Width
+ parameter sw = 4) // Number of Select Lines
+
+ (input clk_i,
+ input rst_i,
+
+ // Master Interface
+ input [dw-1:0] m0_dat_i,
+ output [dw-1:0] m0_dat_o,
+ input [aw-1:0] m0_adr_i,
+ input [sw-1:0] m0_sel_i,
+ input m0_we_i,
+ input m0_cyc_i,
+ input m0_stb_i,
+ output m0_ack_o,
+ output m0_err_o,
+ output m0_rty_o,
+
+ // Slave Interfaces
+ input [dw-1:0] s0_dat_i,
+ output [dw-1:0] s0_dat_o,
+ output [aw-1:0] s0_adr_o,
+ output [sw-1:0] s0_sel_o,
+ output s0_we_o,
+ output s0_cyc_o,
+ output s0_stb_o,
+ input s0_ack_i,
+ input s0_err_i,
+ input s0_rty_i,
+
+ input [dw-1:0] s1_dat_i,
+ output [dw-1:0] s1_dat_o,
+ output [aw-1:0] s1_adr_o,
+ output [sw-1:0] s1_sel_o,
+ output s1_we_o,
+ output s1_cyc_o,
+ output s1_stb_o,
+ input s1_ack_i,
+ input s1_err_i,
+ input s1_rty_i,
+
+ input [dw-1:0] s2_dat_i,
+ output [dw-1:0] s2_dat_o,
+ output [aw-1:0] s2_adr_o,
+ output [sw-1:0] s2_sel_o,
+ output s2_we_o,
+ output s2_cyc_o,
+ output s2_stb_o,
+ input s2_ack_i,
+ input s2_err_i,
+ input s2_rty_i,
+
+ input [dw-1:0] s3_dat_i,
+ output [dw-1:0] s3_dat_o,
+ output [aw-1:0] s3_adr_o,
+ output [sw-1:0] s3_sel_o,
+ output s3_we_o,
+ output s3_cyc_o,
+ output s3_stb_o,
+ input s3_ack_i,
+ input s3_err_i,
+ input s3_rty_i,
+
+ input [dw-1:0] s4_dat_i,
+ output [dw-1:0] s4_dat_o,
+ output [aw-1:0] s4_adr_o,
+ output [sw-1:0] s4_sel_o,
+ output s4_we_o,
+ output s4_cyc_o,
+ output s4_stb_o,
+ input s4_ack_i,
+ input s4_err_i,
+ input s4_rty_i,
+
+ input [dw-1:0] s5_dat_i,
+ output [dw-1:0] s5_dat_o,
+ output [aw-1:0] s5_adr_o,
+ output [sw-1:0] s5_sel_o,
+ output s5_we_o,
+ output s5_cyc_o,
+ output s5_stb_o,
+ input s5_ack_i,
+ input s5_err_i,
+ input s5_rty_i,
+
+ input [dw-1:0] s6_dat_i,
+ output [dw-1:0] s6_dat_o,
+ output [aw-1:0] s6_adr_o,
+ output [sw-1:0] s6_sel_o,
+ output s6_we_o,
+ output s6_cyc_o,
+ output s6_stb_o,
+ input s6_ack_i,
+ input s6_err_i,
+ input s6_rty_i,
+
+ input [dw-1:0] s7_dat_i,
+ output [dw-1:0] s7_dat_o,
+ output [aw-1:0] s7_adr_o,
+ output [sw-1:0] s7_sel_o,
+ output s7_we_o,
+ output s7_cyc_o,
+ output s7_stb_o,
+ input s7_ack_i,
+ input s7_err_i,
+ input s7_rty_i);
+
+ // ////////////////////////////////////////////////////////////////
+ //
+ // Local wires
+ //
+
+ wire [7:0] ssel_dec;
+ reg [dw-1:0] i_dat_s; // internal share bus , slave data to
master
+
+ // Master output Interface
+ assign m0_dat_o = i_dat_s;
+
+ always @*
+ case(ssel_dec)
+ 1 : i_dat_s <= s0_dat_i;
+ 2 : i_dat_s <= s1_dat_i;
+ 4 : i_dat_s <= s2_dat_i;
+ 8 : i_dat_s <= s3_dat_i;
+ 16 : i_dat_s <= s4_dat_i;
+ 32 : i_dat_s <= s5_dat_i;
+ 64 : i_dat_s <= s6_dat_i;
+ 128 : i_dat_s <= s7_dat_i;
+ default : i_dat_s <= s0_dat_i;
+ endcase // case(ssel_dec)
+
+ assign {m0_ack_o, m0_err_o, m0_rty_o}
+ = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i |
s6_ack_i | s7_ack_i ,
+ s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i |
s6_err_i | s7_err_i ,
+ s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i |
s6_rty_i | s7_rty_i };
+
+ // Slave output interfaces
+ assign s0_adr_o = m0_adr_i;
+ assign s0_sel_o = m0_sel_i;
+ assign s0_dat_o = m0_dat_i;
+ assign s0_we_o = m0_we_i;
+ assign s0_cyc_o = m0_cyc_i;
+ assign s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0];
+
+ assign s1_adr_o = m0_adr_i;
+ assign s1_sel_o = m0_sel_i;
+ assign s1_dat_o = m0_dat_i;
+ assign s1_we_o = m0_we_i;
+ assign s1_cyc_o = m0_cyc_i;
+ assign s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1];
+
+ assign s2_adr_o = m0_adr_i;
+ assign s2_sel_o = m0_sel_i;
+ assign s2_dat_o = m0_dat_i;
+ assign s2_we_o = m0_we_i;
+ assign s2_cyc_o = m0_cyc_i;
+ assign s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2];
+
+ assign s3_adr_o = m0_adr_i;
+ assign s3_sel_o = m0_sel_i;
+ assign s3_dat_o = m0_dat_i;
+ assign s3_we_o = m0_we_i;
+ assign s3_cyc_o = m0_cyc_i;
+ assign s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3];
+
+ assign s4_adr_o = m0_adr_i;
+ assign s4_sel_o = m0_sel_i;
+ assign s4_dat_o = m0_dat_i;
+ assign s4_we_o = m0_we_i;
+ assign s4_cyc_o = m0_cyc_i;
+ assign s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4];
+
+ assign s5_adr_o = m0_adr_i;
+ assign s5_sel_o = m0_sel_i;
+ assign s5_dat_o = m0_dat_i;
+ assign s5_we_o = m0_we_i;
+ assign s5_cyc_o = m0_cyc_i;
+ assign s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5];
+
+ assign s6_adr_o = m0_adr_i;
+ assign s6_sel_o = m0_sel_i;
+ assign s6_dat_o = m0_dat_i;
+ assign s6_we_o = m0_we_i;
+ assign s6_cyc_o = m0_cyc_i;
+ assign s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6];
+
+ assign s7_adr_o = m0_adr_i;
+ assign s7_sel_o = m0_sel_i;
+ assign s7_dat_o = m0_dat_i;
+ assign s7_we_o = m0_we_i;
+ assign s7_cyc_o = m0_cyc_i;
+ assign s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7];
+
+ // Address decode logic
+ // WARNING -- must make sure these are mutually exclusive!
+ assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] ==
s0_addr);
+ assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] ==
s1_addr);
+ assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - s27_addr_w ] ==
s2_addr);
+ assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - s27_addr_w ] ==
s3_addr);
+ assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - s27_addr_w ] ==
s4_addr);
+ assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - s27_addr_w ] ==
s5_addr);
+ assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - s27_addr_w ] ==
s6_addr);
+ assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - s27_addr_w ] ==
s7_addr);
+
+endmodule // wb_1master
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