ARM simulator: handle COFF architecture limitations.

[Nick Clifton]

Hi Guys,

  I am checking in the patch below to allow the ARM simulator to
  correctly handle xscale-coff binaries.  The problem was that the
  COFF header does not have enough bits to distinguish between v5 ARM
  binaries and v5T, v5TE and XScale binaries.  So it would always
  default to v5, and the simulator would refuse to emulate
  instructions in the higher architectures.

Cheers
        Nick

2002-02-04  Nick Clifton  <address@hidden>

        * wrapper.c: If a v5 architecture is detected, assume it might be
        an XScale binary, since there is no way to distinguish between
        the two in the COFF file format.

Index: sim/arm/wrapper.c
===================================================================
RCS file: /cvs/src/src/sim/arm/wrapper.c,v
retrieving revision 1.15
diff -c -3 -p -w -r1.15 wrapper.c
*** wrapper.c   2002/01/09 15:08:21     1.15
--- wrapper.c   2002/02/04 16:23:19
*************** sim_create_inferior (sd, abfd, argv, env
*** 234,239 ****
--- 234,248 ----
        break;
  
      case bfd_mach_arm_5:
+       /* This is a special case in order to support COFF based ARM toolchains.
+        The COFF header does not have enough room to store all the different
+        kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
+        to v5.  (See coff_set_flags() in bdf/coffcode.h).  So if we see a v5
+        machine type here, we assume it could be any of the above architectures
+        and so select the most feature-full.  */
+       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | 
ARM_XScale_Prop);
+       break;
+ 
      case bfd_mach_arm_5T:
        ARMul_SelectProcessor (state, ARM_v5_Prop);
        break;