[PATCH] Named symbol references

[Alex Rozenman]

Hello bison team.

I would like to submit a patch adding some kind of named symbol references
in input grammar. It looks like this:

tchk_definition
  : SETUP(kw) '(' timing_check_event(dat) ',' timing_check_event(ref) ','
timing_check_limit(lmt)
    notify_register_arg(reg) ')'
    {
      vcLinkTchk(accSetup, $ref, $dat, $lmt, $reg, vsc_scopeG, vsc_specifyG,
$kw.lineNum, $kw.srcInfo);
    }

@name (location info) is also supported.

This functionality has been already tested and used in my company for many
(5+) years, the original change was
done on 1.75 version. There are some big scale parsers (Verilog, Verilog
2001, VHDL) implemented using this syntax.

I understand that at least, documentaion and tests are missing. This is my
first time I am trying to contribute to bison,
so please provide me additional info about the process.

I attached the git generated patch mail.

-- 
Best regards,
Alex Rozenman (address@hidden).

0001-named-symbol-references-implemented.patch
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