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[avr-gcc-list] [patch] avr-libc ATmega128 include file
|
From: |
Svein E. Seldal |
|
Subject: |
[avr-gcc-list] [patch] avr-libc ATmega128 include file |
|
Date: |
Mon, 26 Aug 2002 16:45:00 +0200 |
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User-agent: |
Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.1b) Gecko/20020721 |
Hello,
I've updated the include/avr/iom128.h file to have all the bits and port
definitions found in the latest ATmega128 datasheet.
Regads,
Svein
ChangeLog:
2002-08-26 Svein E. Seldal <address@hidden>
* include/avr/iom128.h: Updated include definitions
against the latest datasheet from Atmel.
Index: include/avr/iom128.h
===================================================================
RCS file: /cvsroot/avr-libc/avr-libc/include/avr/iom128.h,v
retrieving revision 1.1
diff -c -3 -p -r1.1 iom128.h
*** include/avr/iom128.h 5 Jul 2002 20:38:44 -0000 1.1
--- include/avr/iom128.h 26 Aug 2002 14:40:24 -0000
***************
*** 30,36 ****
#include <avr/sfr_defs.h>
! /* I/O registers */
/* Input Pins, Port F */
#define PINF _SFR_IO8(0x00)
--- 30,38 ----
#include <avr/sfr_defs.h>
! /*
! ** I/O registers
! */
/* Input Pins, Port F */
#define PINF _SFR_IO8(0x00)
***************
*** 45,56 ****
#define PORTE _SFR_IO8(0x03)
/* ADC Data Register */
! #define ADCW _SFR_IO16(0x04)
! #define ADCL _SFR_IO8(0x04)
! #define ADCH _SFR_IO8(0x05)
/* ADC Control and status register */
! #define ADCSR _SFR_IO8(0x06)
/* ADC Multiplexer select */
#define ADMUX _SFR_IO8(0x07)
--- 47,58 ----
#define PORTE _SFR_IO8(0x03)
/* ADC Data Register */
! #define ADC _SFR_IO16(0x04)
! #define ADCL _SFR_IO8(0x04)
! #define ADCH _SFR_IO8(0x05)
/* ADC Control and status register */
! #define ADCSRA _SFR_IO8(0x06)
/* ADC Multiplexer select */
#define ADMUX _SFR_IO8(0x07)
***************
*** 122,128 ****
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
! #define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
--- 124,130 ----
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
! #define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
***************
*** 145,166 ****
#define TCCR2 _SFR_IO8(0x25)
/* T/C 1 Input Capture Register */
! #define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare Register B */
! #define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
! #define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
! #define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
--- 147,168 ----
#define TCCR2 _SFR_IO8(0x25)
/* T/C 1 Input Capture Register */
! #define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare Register B */
! #define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
! #define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
! #define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
***************
*** 183,189 ****
#define TCCR0 _SFR_IO8(0x33)
/* MCU Status Register */
! #define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
--- 185,191 ----
#define TCCR0 _SFR_IO8(0x33)
/* MCU Status Register */
! #define MCUCSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
***************
*** 210,223 ****
#define XDIV _SFR_IO8(0x3C)
/* Stack Pointer */
! #define SP _SFR_IO16(0x3D)
! #define SPL _SFR_IO8(0x3D)
! #define SPH _SFR_IO8(0x3E)
/* Status REGister */
#define SREG _SFR_IO8(0x3F)
! /* Extended I/O registers */
/* Data Direction Register, Port F */
#define DDRF _SFR_MEM8(0x61)
--- 212,228 ----
#define XDIV _SFR_IO8(0x3C)
/* Stack Pointer */
! #define SP _SFR_IO16(0x3D)
! #define SPL _SFR_IO8(0x3D)
! #define SPH _SFR_IO8(0x3E)
/* Status REGister */
#define SREG _SFR_IO8(0x3F)
!
! /*
! ** Extended I/O registers
! */
/* Data Direction Register, Port F */
#define DDRF _SFR_MEM8(0x61)
***************
*** 235,241 ****
#define PORTG _SFR_MEM8(0x65)
/* Store Program Memory Control Register */
! #define SPMCR _SFR_MEM8(0x68)
/* External Interrupt Control Register A */
#define EICRA _SFR_MEM8(0x6A)
--- 240,247 ----
#define PORTG _SFR_MEM8(0x65)
/* Store Program Memory Control Register */
! #define SPMCSR _SFR_MEM8(0x68)
! #define SPMCR _SFR_MEM8(0x68)
/* External Interrupt Control Register A */
#define EICRA _SFR_MEM8(0x6A)
***************
*** 265,271 ****
#define TWCR _SFR_MEM8(0x74)
/* Time Counter 1 Output Compare Register C */
! #define OCR1C _SFR_MEM16(0x78)
#define OCR1CL _SFR_MEM8(0x78)
#define OCR1CH _SFR_MEM8(0x79)
--- 271,277 ----
#define TWCR _SFR_MEM8(0x74)
/* Time Counter 1 Output Compare Register C */
! #define OCR1C _SFR_MEM16(0x78)
#define OCR1CL _SFR_MEM8(0x78)
#define OCR1CH _SFR_MEM8(0x79)
***************
*** 279,305 ****
#define ETIMSK _SFR_MEM8(0x7D)
/* Timer/Counter 3 Input Capture Register */
! #define ICR3 _SFR_MEM16(0x80)
#define ICR3L _SFR_MEM8(0x80)
#define ICR3H _SFR_MEM8(0x81)
/* Timer/Counter 3 Output Compare Register C */
! #define OCR3C _SFR_MEM16(0x82)
#define OCR3CL _SFR_MEM8(0x82)
#define OCR3CH _SFR_MEM8(0x83)
/* Timer/Counter 3 Output Compare Register B */
! #define OCR3B _SFR_MEM16(0x84)
#define OCR3BL _SFR_MEM8(0x84)
#define OCR3BH _SFR_MEM8(0x85)
/* Timer/Counter 3 Output Compare Register A */
! #define OCR3A _SFR_MEM16(0x86)
#define OCR3AL _SFR_MEM8(0x86)
#define OCR3AH _SFR_MEM8(0x87)
/* Timer/Counter 3 Counter Register */
! #define TCNT3 _SFR_MEM16(0x88)
#define TCNT3L _SFR_MEM8(0x88)
#define TCNT3H _SFR_MEM8(0x89)
--- 285,311 ----
#define ETIMSK _SFR_MEM8(0x7D)
/* Timer/Counter 3 Input Capture Register */
! #define ICR3 _SFR_MEM16(0x80)
#define ICR3L _SFR_MEM8(0x80)
#define ICR3H _SFR_MEM8(0x81)
/* Timer/Counter 3 Output Compare Register C */
! #define OCR3C _SFR_MEM16(0x82)
#define OCR3CL _SFR_MEM8(0x82)
#define OCR3CH _SFR_MEM8(0x83)
/* Timer/Counter 3 Output Compare Register B */
! #define OCR3B _SFR_MEM16(0x84)
#define OCR3BL _SFR_MEM8(0x84)
#define OCR3BH _SFR_MEM8(0x85)
/* Timer/Counter 3 Output Compare Register A */
! #define OCR3A _SFR_MEM16(0x86)
#define OCR3AL _SFR_MEM8(0x86)
#define OCR3AH _SFR_MEM8(0x87)
/* Timer/Counter 3 Counter Register */
! #define TCNT3 _SFR_MEM16(0x88)
#define TCNT3L _SFR_MEM8(0x88)
#define TCNT3H _SFR_MEM8(0x89)
***************
*** 318,327 ****
/* USART0 Control and Status Register C */
#define UCSR0C _SFR_MEM8(0x95)
! /* USART1 Baud Rate Register High */
#define UBRR1H _SFR_MEM8(0x98)
-
- /* USART1 Baud Rate Register Low*/
#define UBRR1L _SFR_MEM8(0x99)
/* USART1 Control and Status Register B */
--- 324,332 ----
/* USART0 Control and Status Register C */
#define UCSR0C _SFR_MEM8(0x95)
! /* USART1 Baud Rate Register */
! #define UBRR1 _SFR_MEM16(0x98)
#define UBRR1H _SFR_MEM8(0x98)
#define UBRR1L _SFR_MEM8(0x99)
/* USART1 Control and Status Register B */
***************
*** 337,344 ****
#define UCSR1C _SFR_MEM8(0x9D)
! /* Interrupt vectors */
!
#define SIG_INTERRUPT0 _VECTOR(1)
#define SIG_INTERRUPT1 _VECTOR(2)
#define SIG_INTERRUPT2 _VECTOR(3)
--- 342,350 ----
#define UCSR1C _SFR_MEM8(0x9D)
! /*
! ** Interrupt vectors
! */
#define SIG_INTERRUPT0 _VECTOR(1)
#define SIG_INTERRUPT1 _VECTOR(2)
#define SIG_INTERRUPT2 _VECTOR(3)
***************
*** 377,610 ****
#define _VECTORS_SIZE 140
/*
! The Register Bit names are represented by their bit number (0-7).
*/
- /* 2-wire Control Register */
- #define TWINT 7
- #define TWEA 6
- #define TWSTA 5
- #define TWSTO 4
- #define TWWC 3
- #define TWEN 2
- #define TWIE 0
-
- /* 2-wire Address Register */
- #define TWA6 7
- #define TWA5 6
- #define TWA4 5
- #define TWA3 4
- #define TWA2 3
- #define TWA1 2
- #define TWA0 1
- #define TWGCE 0
-
- /* 2-wire Status Register */
- #define TWS7 7
- #define TWS6 6
- #define TWS5 5
- #define TWS4 4
- #define TWS3 3
- #define TWPS1 1
- #define TWPS0 0
-
- /* External Memory Control Register A */
- #define SRL2 6
- #define SRL1 5
- #define SRL0 4
- #define SRW01 3
- #define SRW00 2
- #define SRW11 1
-
- /* External Memory Control Register B */
- #define XMBK 7
- #define XMM2 2
- #define XMM1 1
- #define XMM0 0
-
- /* XDIV Divide control register*/
- #define XDIVEN 7
- #define XDIV6 6
- #define XDIV5 5
- #define XDIV4 4
- #define XDIV3 3
- #define XDIV2 2
- #define XDIV1 1
- #define XDIV0 0
-
- /* RAM Page Z select register */
- #define RAMPZ0 0
-
- /* External Interrupt Control Register A */
- #define ISC31 7
- #define ISC30 6
- #define ISC21 5
- #define ISC20 4
- #define ISC11 3
- #define ISC10 2
- #define ISC01 1
- #define ISC00 0
-
- /* External Interrupt Control Register B */
- #define ISC71 7
- #define ISC70 6
- #define ISC61 5
- #define ISC60 4
- #define ISC51 3
- #define ISC50 2
- #define ISC41 1
- #define ISC40 0
-
- /* Store Program Memory Control Register */
- #define SPMIE 7
- #define RWWSB 6
- #define RWWSRE 4
- #define BLBSET 3
- #define PGWRT 2
- #define PGERS 1
- #define SPMEN 0
-
- /* External Interrupt MaSK register */
- #define INT7 7
- #define INT6 6
- #define INT5 5
- #define INT4 4
- #define INT3 3
- #define INT2 2
- #define INT1 1
- #define INT0 0
-
- /* External Interrupt Flag Register */
- #define INTF7 7
- #define INTF6 6
- #define INTF5 5
- #define INTF4 4
-
- /* Timer/Counter Interrupt MaSK register */
- #define OCIE2 7
- #define TOIE2 6
- #define TICIE1 5
- #define OCIE1A 4
- #define OCIE1B 3
- #define TOIE1 2
- #define OCIE0 1
- #define TOIE0 0
-
- /* Timer/Counter Interrupt Flag Register */
- #define OCF2 7
- #define TOV2 6
- #define ICF1 5
- #define OCF1A 4
- #define OCF1B 3
- #define TOV1 2
- #define OCF0 1
- #define TOV0 0
-
- /* Extended Timer Interrupt MaSK register */
- #define TICIE3 5
- #define OCIE3A 4
- #define OCIE3B 3
- #define TOIE3 2
- #define OCIE3C 1
- #define OCIE1C 0
-
- /* Extended Timer Interrupt Flag Register */
- #define ICF3 5
- #define OCF3A 4
- #define OCF3B 3
- #define TOV3 2
- #define OCF3C 1
- #define OCF1C 0
-
- /* MCU general Control Register */
- #define SRE 7
- #define SRW 6
- #define SE 5
- #define SM1 4
- #define SM0 3
- #define SM2 2
- #define IVSEL 1
- #define IVCE 0
-
- /* MCU Status Register */
- #define JTD 7
- #define JTRF 4
- #define WDRF 3
- #define BORF 2
- #define EXTRF 1
- #define PORF 0
-
- /* Timer/Counter Control Register */
- #define FOC 7
- #define WGM0 6
- #define COM1 5
- #define COM0 4
- #define WGM1 3
- #define CS2 2
- #define CS1 1
- #define CS0 0
-
- /* Timer/Counter 0 Asynchronous Control & Status Register */
- #define AS0 3
- #define TCN0UB 2
- #define OCR0UB 1
- #define TCR0UB 0
-
- /* Timer/Counter Control Register A */
- #define COMA1 7
- #define COMA0 6
- #define COMB1 5
- #define COMB0 4
- #define COMC1 3
- #define COMC0 2
- #define WGMA1 1
- #define WGMA0 0
-
- /* Timer/Counter Control and Status Register B */
- #define ICNC 7
- #define ICES 6
- #define WGMB3 4
- #define WGMB2 3
- #define CSB2 2
- #define CSB1 1
- #define CSB0 0
-
- /* Timer/Counter Control Register C */
- #define FOCA 7
- #define FOCB 6
- #define FOCC 5
-
- /* On-chip Debug Register */
- #define OCDR7 7
- #define OCDR6 6
- #define OCDR5 5
- #define OCDR4 4
- #define OCDR3 3
- #define OCDR2 2
- #define OCDR1 1
- #define OCDR0 0
-
- /* Watchdog Timer Control Register */
- #define WDCE 4
- #define WDE 3
- #define WDP2 2
- #define WDP1 1
- #define WDP0 0
-
- /* Special Function I/O Register */
- #define TSM 7
- #define ADHSM 4
- #define ACME 3
- #define PUD 2
- #define PSR0 1
- #define PSR321 0
-
- /* EEPROM Control Register */
- #define EERIE 3
- #define EEMWE 2
- #define EEWE 1
- #define EERE 0
-
/* Port Data Register */
#define PORT7 7
#define PORT6 6
--- 383,391 ----
#define _VECTORS_SIZE 140
/*
! ** Generic def's
*/
/* Port Data Register */
#define PORT7 7
#define PORT6 6
***************
*** 635,674 ****
#define PIN1 1
#define PIN0 0
- /* Status Register */
- #define SREG_I 7
- #define SREG_T 6
- #define SREG_H 5
- #define SREG_S 4
- #define SREG_V 3
- #define SREG_N 2
- #define SREG_Z 1
- #define SREG_C 0
-
- /* SPI Status Register */
- #define SPIF 7
- #define WCOL 6
- #define SPI2X 0
-
- /* SPI Control Register */
- #define SPIE 7
- #define SPE 6
- #define DORD 5
- #define MSTR 4
- #define CPOL 3
- #define CPHA 2
- #define SPR1 1
- #define SPR0 0
-
- /* USART Register C */
- #define UMSEL 6
- #define UPM1 5
- #define UPM0 4
- #define USBS 3
- #define UCSZ1 2
- #define UCSZ0 1
- #define UCPOL 0
-
/* USART Status Register A */
#define RXC 7
#define TXC 6
--- 416,421 ----
***************
*** 685,705 ****
#define UDRIE 5
#define RXEN 4
#define TXEN 3
! #define UCSZ 2
#define RXB8 1
#define TXB8 0
! /* Analog Comparator Control and Status Register */
! #define ACD 7
! #define ACBG 6
! #define ACO 5
! #define ACI 4
! #define ACIE 3
! #define ACIC 2
! #define ACIS1 1
! #define ACIS0 0
! /* ADC Control and status register */
#define ADEN 7
#define ADSC 6
#define ADFR 5
--- 432,496 ----
#define UDRIE 5
#define RXEN 4
#define TXEN 3
! #define UCSZ2 2
#define RXB8 1
#define TXB8 0
! /* USART Register C */
! #define UMSEL 6
! #define UPM1 5
! #define UPM0 4
! #define USBS 3
! #define UCSZ1 2
! #define UCSZ0 1
! #define UCPOL 0
!
! /*
! ** SPECIFIC REGISTERS
! */
!
! /* Port F Input Pins - PINF */
! #define PINF7 7
! #define PINF6 6
! #define PINF5 5
! #define PINF4 4
! #define PINF3 3
! #define PINF2 2
! #define PINF1 1
! #define PINF0 0
!
! /* Port E Input Pins - PINE */
! #define PINE7 7
! #define PINE6 6
! #define PINE5 5
! #define PINE4 4
! #define PINE3 3
! #define PINE2 2
! #define PINE1 1
! #define PINE0 0
!
! /* Port E Data Direction Register - DDRE */
! #define DDE7 7
! #define DDE6 6
! #define DDE5 5
! #define DDE4 4
! #define DDE3 3
! #define DDE2 2
! #define DDE1 1
! #define DDE0 0
!
! /* Port E Data Register - PORTE */
! #define PORTE7 7
! #define PORTE6 6
! #define PORTE5 5
! #define PORTE4 4
! #define PORTE3 3
! #define PORTE2 2
! #define PORTE1 1
! #define PORTE0 0
!
! /* ADC Control and Status Register A - ADCSRA */
#define ADEN 7
#define ADSC 6
#define ADFR 5
***************
*** 709,715 ****
#define ADPS1 1
#define ADPS0 0
! /* ADC Multiplexer select */
#define REFS1 7
#define REFS0 6
#define ADLAR 5
--- 500,506 ----
#define ADPS1 1
#define ADPS0 0
! /* ADC Multiplexer select - ADMUX */
#define REFS1 7
#define REFS0 6
#define ADLAR 5
***************
*** 718,723 ****
--- 509,1037 ----
#define MUX2 2
#define MUX1 1
#define MUX0 0
+
+ /* Analog Comparator Control and Status Register - ACSR */
+ #define ACD 7
+ #define ACBG 6
+ #define ACO 5
+ #define ACI 4
+ #define ACIE 3
+ #define ACIC 2
+ #define ACIS1 1
+ #define ACIS0 0
+
+ /* USART Control Register B - UCSR0B */
+ #define RXCIE0 7
+ #define TXCIE0 6
+ #define UDRIE0 5
+ #define RXEN0 4
+ #define TXEN0 3
+ #define UCSZ02 2
+ #define RXB80 1
+ #define TXB80 0
+
+ /* USART Status Register A - UCSR0A */
+ #define RXC0 7
+ #define TXC0 6
+ #define UDRE0 5
+ #define FE0 4
+ #define DOR0 3
+ #define UPE0 2
+ #define U2X0 1
+ #define MPCM0 0
+
+ /* SPI Control Register - SPCR */
+ #define SPIE 7
+ #define SPE 6
+ #define DORD 5
+ #define MSTR 4
+ #define CPOL 3
+ #define CPHA 2
+ #define SPR1 1
+ #define SPR0 0
+
+ /* SPI Status Register - SPSR */
+ #define SPIF 7
+ #define WCOL 6
+ #define SPI2X 0
+
+ /* Port D Input Pins - PIND */
+ #define PIND7 7
+ #define PIND6 6
+ #define PIND5 5
+ #define PIND4 4
+ #define PIND3 3
+ #define PIND2 2
+ #define PIND1 1
+ #define PIND0 0
+
+ /* Port D Data Direction Register - DDRD */
+ #define DDD7 7
+ #define DDD6 6
+ #define DDD5 5
+ #define DDD4 4
+ #define DDD3 3
+ #define DDD2 2
+ #define DDD1 1
+ #define DDD0 0
+
+ /* Port D Data Register - PORTD */
+ #define PORTD7 7
+ #define PORTD6 6
+ #define PORTD5 5
+ #define PORTD4 4
+ #define PORTD3 3
+ #define PORTD2 2
+ #define PORTD1 1
+ #define PORTD0 0
+
+ /* Port C Input Pins - PINC */
+ #define PINC7 7
+ #define PINC6 6
+ #define PINC5 5
+ #define PINC4 4
+ #define PINC3 3
+ #define PINC2 2
+ #define PINC1 1
+ #define PINC0 0
+
+ /* Port C Data Direction Register - DDRC */
+ #define DDC7 7
+ #define DDC6 6
+ #define DDC5 5
+ #define DDC4 4
+ #define DDC3 3
+ #define DDC2 2
+ #define DDC1 1
+ #define DDC0 0
+
+ /* Port C Data Register - PORTC */
+ #define PORTC7 7
+ #define PORTC6 6
+ #define PORTC5 5
+ #define PORTC4 4
+ #define PORTC3 3
+ #define PORTC2 2
+ #define PORTC1 1
+ #define PORTC0 0
+
+ /* Port B Input Pins - PINB */
+ #define PINB7 7
+ #define PINB6 6
+ #define PINB5 5
+ #define PINB4 4
+ #define PINB3 3
+ #define PINB2 2
+ #define PINB1 1
+ #define PINB0 0
+
+ /* Port B Data Direction Register - DDRB */
+ #define DDB7 7
+ #define DDB6 6
+ #define DDB5 5
+ #define DDB4 4
+ #define DDB3 3
+ #define DDB2 2
+ #define DDB1 1
+ #define DDB0 0
+
+ /* Port B Data Register - PORTB */
+ #define PORTB7 7
+ #define PORTB6 6
+ #define PORTB5 5
+ #define PORTB4 4
+ #define PORTB3 3
+ #define PORTB2 2
+ #define PORTB1 1
+ #define PORTB0 0
+
+ /* Port A Input Pins - PINA */
+ #define PINA7 7
+ #define PINA6 6
+ #define PINA5 5
+ #define PINA4 4
+ #define PINA3 3
+ #define PINA2 2
+ #define PINA1 1
+ #define PINA0 0
+
+ /* Port A Data Direction Register - DDRA */
+ #define DDA7 7
+ #define DDA6 6
+ #define DDA5 5
+ #define DDA4 4
+ #define DDA3 3
+ #define DDA2 2
+ #define DDA1 1
+ #define DDA0 0
+
+ /* Port A Data Register - PORTA */
+ #define PORTA7 7
+ #define PORTA6 6
+ #define PORTA5 5
+ #define PORTA4 4
+ #define PORTA3 3
+ #define PORTA2 2
+ #define PORTA1 1
+ #define PORTA0 0
+
+ /* EEPROM Control Register - EECR */
+ #define EERIE 3
+ #define EEMWE 2
+ #define EEWE 1
+ #define EERE 0
+
+ /* Special Function I/O Register - SFIOR */
+ #define TSM 7
+ #define ADHSM 4
+ #define ACME 3
+ #define PUD 2
+ #define PSR0 1
+ #define PSR321 0
+
+ /* Watchdog Timer Control Register - WDTCR */
+ #define WDCE 4
+ #define WDE 3
+ #define WDP2 2
+ #define WDP1 1
+ #define WDP0 0
+
+ /* On-chip Debug Register - OCDR */
+ #define IDRD 7
+ #define OCDR7 7
+ #define OCDR6 6
+ #define OCDR5 5
+ #define OCDR4 4
+ #define OCDR3 3
+ #define OCDR2 2
+ #define OCDR1 1
+ #define OCDR0 0
+
+ /* Timer/Counter Control Register - TCCR2 */
+ #define FOC2 7
+ #define WGM20 6
+ #define COM21 5
+ #define COM20 4
+ #define WGM21 3
+ #define CS22 2
+ #define CS21 1
+ #define CS20 0
+
+ /* Timer/Counter Control and Status Register B - TCCR1B */
+ #define ICNC1 7
+ #define ICES1 6
+ #define WGM13 4
+ #define WGM12 3
+ #define CS12 2
+ #define CS11 1
+ #define CS10 0
+
+ /* Timer/Counter Control Register A - TCCR1A */
+ #define COM1A1 7
+ #define COM1A0 6
+ #define COM1B1 5
+ #define COM1B0 4
+ #define COM1C1 3
+ #define COM1C0 2
+ #define WGM11 1
+ #define WGM10 0
+
+ /* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */
+ #define AS0 3
+ #define TCN0UB 2
+ #define OCR0UB 1
+ #define TCR0UB 0
+
+ /* Timer/Counter Control Register - TCCR0 */
+ #define FOC0 7
+ #define WGM00 6
+ #define COM01 5
+ #define COM00 4
+ #define WGM01 3
+ #define CS02 2
+ #define CS01 1
+ #define CS00 0
+
+ /* MCU Status Register - MCUCSR */
+ #define JTD 7
+ #define JTRF 4
+ #define WDRF 3
+ #define BORF 2
+ #define EXTRF 1
+ #define PORF 0
+
+ /* MCU general Control Register - MCUCR */
+ #define SRE 7
+ #define SRW10 6
+ #define SE 5
+ #define SM1 4
+ #define SM0 3
+ #define SM2 2
+ #define IVSEL 1
+ #define IVCE 0
+
+ /* Timer/Counter Interrupt Flag Register - TIFR */
+ #define OCF2 7
+ #define TOV2 6
+ #define ICF1 5
+ #define OCF1A 4
+ #define OCF1B 3
+ #define TOV1 2
+ #define OCF0 1
+ #define TOV0 0
+
+ /* Timer/Counter Interrupt Mask register - TIMSK */
+ #define OCIE2 7
+ #define TOIE2 6
+ #define TICIE1 5
+ #define OCIE1A 4
+ #define OCIE1B 3
+ #define TOIE1 2
+ #define OCIE0 1
+ #define TOIE0 0
+
+ /* External Interrupt Flag Register - EIFR */
+ #define INTF7 7
+ #define INTF6 6
+ #define INTF5 5
+ #define INTF4 4
+ #define INTF3 3
+ #define INTF2 2
+ #define INTF1 1
+ #define INTF0 0
+
+ /* External Interrupt Mask register - EIMSK */
+ #define INT7 7
+ #define INT6 6
+ #define INT5 5
+ #define INT4 4
+ #define INT3 3
+ #define INT2 2
+ #define INT1 1
+ #define INT0 0
+
+ /* External Interrupt Control Register B - EICRB */
+ #define ISC71 7
+ #define ISC70 6
+ #define ISC61 5
+ #define ISC60 4
+ #define ISC51 3
+ #define ISC50 2
+ #define ISC41 1
+ #define ISC40 0
+
+ /* RAM Page Z select register - RAMPZ */
+ #define RAMPZ0 0
+
+ /* XDIV Divide control register - XDIV */
+ #define XDIVEN 7
+ #define XDIV6 6
+ #define XDIV5 5
+ #define XDIV4 4
+ #define XDIV3 3
+ #define XDIV2 2
+ #define XDIV1 1
+ #define XDIV0 0
+
+ /* Status Register - SREG */
+ #define SREG_I 7
+ #define SREG_T 6
+ #define SREG_H 5
+ #define SREG_S 4
+ #define SREG_V 3
+ #define SREG_N 2
+ #define SREG_Z 1
+ #define SREG_C 0
+
+ /* Port F Data Direction Register - DDRF */
+ #define DDF7 7
+ #define DDF6 6
+ #define DDF5 5
+ #define DDF4 4
+ #define DDF3 3
+ #define DDF2 2
+ #define DDF1 1
+ #define DDF0 0
+
+ /* Port F Data Register - PORTF */
+ #define PORTF7 7
+ #define PORTF6 6
+ #define PORTF5 5
+ #define PORTF4 4
+ #define PORTF3 3
+ #define PORTF2 2
+ #define PORTF1 1
+ #define PORTF0 0
+
+ /* Port G Input Pins - PING */
+ #define PING4 4
+ #define PING3 3
+ #define PING2 2
+ #define PING1 1
+ #define PING0 0
+
+ /* Port G Data Direction Register - DDRG */
+ #define DDG4 4
+ #define DDG3 3
+ #define DDG2 2
+ #define DDG1 1
+ #define DDG0 0
+
+ /* Port G Data Register - PORTG */
+ #define PORTG4 4
+ #define PORTG3 3
+ #define PORTG2 2
+ #define PORTG1 1
+ #define PORTG0 0
+
+ /* Store Program Memory Control Register - SPMCSR, SPMCR */
+ #define SPMIE 7
+ #define RWWSB 6
+ #define RWWSRE 4
+ #define BLBSET 3
+ #define PGWRT 2
+ #define PGERS 1
+ #define SPMEN 0
+
+ /* External Interrupt Control Register A - EICRA */
+ #define ISC31 7
+ #define ISC30 6
+ #define ISC21 5
+ #define ISC20 4
+ #define ISC11 3
+ #define ISC10 2
+ #define ISC01 1
+ #define ISC00 0
+
+ /* External Memory Control Register B - XMCRB */
+ #define XMBK 7
+ #define XMM2 2
+ #define XMM1 1
+ #define XMM0 0
+
+ /* External Memory Control Register A - XMCRA */
+ #define SRL2 6
+ #define SRL1 5
+ #define SRL0 4
+ #define SRW01 3
+ #define SRW00 2
+ #define SRW11 1
+
+ /* 2-wire Status Register - TWSR */
+ #define TWS7 7
+ #define TWS6 6
+ #define TWS5 5
+ #define TWS4 4
+ #define TWS3 3
+ #define TWPS1 1
+ #define TWPS0 0
+
+ /* 2-wire Address Register - TWAR */
+ #define TWA6 7
+ #define TWA5 6
+ #define TWA4 5
+ #define TWA3 4
+ #define TWA2 3
+ #define TWA1 2
+ #define TWA0 1
+ #define TWGCE 0
+
+ /* 2-wire Control Register - TWCR */
+ #define TWINT 7
+ #define TWEA 6
+ #define TWSTA 5
+ #define TWSTO 4
+ #define TWWC 3
+ #define TWEN 2
+ #define TWIE 0
+
+ /* Timer/Counter Control Register C - TCCR1C */
+ #define FOC1A 7
+ #define FOC1B 6
+ #define FOC1C 5
+
+ /* Extended Timer Interrupt Flag Register - ETIFR */
+ #define ICF3 5
+ #define OCF3A 4
+ #define OCF3B 3
+ #define TOV3 2
+ #define OCF3C 1
+ #define OCF1C 0
+
+ /* Extended Timer Interrupt Mask register - ETIMSK */
+ #define TICIE3 5
+ #define OCIE3A 4
+ #define OCIE3B 3
+ #define TOIE3 2
+ #define OCIE3C 1
+ #define OCIE1C 0
+
+ /* Timer/Counter Control and Status Register B - TCCR3B */
+ #define ICNC3 7
+ #define ICES3 6
+ #define WGM33 4
+ #define WGM32 3
+ #define CS32 2
+ #define CS31 1
+ #define CS30 0
+
+ /* Timer/Counter Control and Status Register A - TCCR3A */
+ #define COM3A1 7
+ #define COM3A0 6
+ #define COM3B1 5
+ #define COM3B0 4
+ #define COM3C1 3
+ #define COM3C0 2
+ #define WGM31 1
+ #define WGM30 0
+
+ /* Timer/Counter Control Register C - TCCR3C */
+ #define FOC3A 7
+ #define FOC3B 6
+ #define FOC3C 5
+
+ /* USART Register C - UCSR0C */
+ #define UMSEL0 6
+ #define UPM01 5
+ #define UPM00 4
+ #define USBS0 3
+ #define UCSZ01 2
+ #define UCSZ00 1
+ #define UCPOL0 0
+
+ /* USART Control Register B - UCSR1B */
+ #define RXCIE1 7
+ #define TXCIE1 6
+ #define UDRIE1 5
+ #define RXEN1 4
+ #define TXEN1 3
+ #define UCSZ12 2
+ #define RXB81 1
+ #define TXB81 0
+
+ /* USART Status Register A - UCSR1A */
+ #define RXC1 7
+ #define TXC1 6
+ #define UDRE1 5
+ #define FE1 4
+ #define DOR1 3
+ #define UPE1 2
+ #define U2X1 1
+ #define MPCM1 0
+
+ /* USART Register C - UCSR1C */
+ #define UMSEL1 6
+ #define UPM11 5
+ #define UPM10 4
+ #define USBS1 3
+ #define UCSZ11 2
+ #define UCSZ10 1
+ #define UCPOL1 0
+
+
+ /*
+ ** Misc. definitions
+ */
/* Pointer definition */
#define XL r26
- [avr-gcc-list] [patch] avr-libc ATmega128 include file,
Svein E. Seldal <=