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[PULL 53/65] target/riscv: add RVA22S64 profile
From: |
Alistair Francis |
Subject: |
[PULL 53/65] target/riscv: add RVA22S64 profile |
Date: |
Wed, 10 Jan 2024 18:57:21 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The RVA22S64 profile consists of the following:
- all mandatory extensions of RVA22U64;
- priv spec v1.12.0;
- satp mode sv39;
- Ssccptr, a cache related named feature that we're assuming always
enable since we don't implement a cache;
- Other named features already implemented: Sstvecd, Sstvala,
Sscounterenw;
- the new Svade named feature that was recently added.
Most of the work is already done, so this patch is enough to implement
the profile.
After this patch, the 'rva22s64' user flag alone can be used with the
rva64i CPU to boot Linux:
-cpu rv64i,rva22s64=true
This is the /proc/cpuinfo with this profile enabled:
# cat /proc/cpuinfo
processor : 0
hart : 0
isa :
rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihintpause_zihpm_zfhmin_zca_zcd_zba_zbb_zbs_zkt_svinval_svpbmt
mmu : sv39
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-26-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 616b091303..a8f4081922 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1559,8 +1559,40 @@ static RISCVCPUProfile RVA22U64 = {
}
};
+/*
+ * As with RVA22U64, RVA22S64 also defines 'named features'.
+ *
+ * Cache related features that we consider enabled since we don't
+ * implement cache: Ssccptr
+ *
+ * Other named features that we already implement: Sstvecd, Sstvala,
+ * Sscounterenw
+ *
+ * Named features that we need to enable: svade
+ *
+ * The remaining features/extensions comes from RVA22U64.
+ */
+static RISCVCPUProfile RVA22S64 = {
+ .parent = &RVA22U64,
+ .name = "rva22s64",
+ .misa_ext = RVS,
+ .priv_spec = PRIV_VERSION_1_12_0,
+ .satp_mode = VM_1_10_SV39,
+ .ext_offsets = {
+ /* rva22s64 exts */
+ CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
+ CPU_CFG_OFFSET(ext_svinval),
+
+ /* rva22s64 named features */
+ CPU_CFG_OFFSET(svade),
+
+ RISCV_PROFILE_EXT_LIST_END
+ }
+};
+
RISCVCPUProfile *riscv_profiles[] = {
&RVA22U64,
+ &RVA22S64,
NULL,
};
--
2.43.0
- [PULL 42/65] target/riscv/tcg: add hash table insert helpers, (continued)
- [PULL 42/65] target/riscv/tcg: add hash table insert helpers, Alistair Francis, 2024/01/10
- [PULL 44/65] target/riscv/tcg: validate profiles during finalize, Alistair Francis, 2024/01/10
- [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion, Alistair Francis, 2024/01/10
- [PULL 46/65] target/riscv: add 'rva22u64' CPU, Alistair Francis, 2024/01/10
- [PULL 47/65] target/riscv: implement svade, Alistair Francis, 2024/01/10
- [PULL 48/65] target/riscv: add priv ver restriction to profiles, Alistair Francis, 2024/01/10
- [PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier, Alistair Francis, 2024/01/10
- [PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit(), Alistair Francis, 2024/01/10
- [PULL 51/65] target/riscv: add satp_mode profile support, Alistair Francis, 2024/01/10
- [PULL 52/65] target/riscv: add 'parent' in profile description, Alistair Francis, 2024/01/10
- [PULL 53/65] target/riscv: add RVA22S64 profile,
Alistair Francis <=
- [PULL 54/65] target/riscv: add rva22s64 cpu, Alistair Francis, 2024/01/10
- [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket, Alistair Francis, 2024/01/10
- [PULL 56/65] linux-headers: Update to Linux v6.7-rc5, Alistair Francis, 2024/01/10
- [PULL 57/65] linux-headers: riscv: add ptrace.h, Alistair Francis, 2024/01/10
- [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct, Alistair Francis, 2024/01/10
- [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4, Alistair Francis, 2024/01/10
- [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0, Alistair Francis, 2024/01/10
- [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize(), Alistair Francis, 2024/01/10
- [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs, Alistair Francis, 2024/01/10
- [PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions, Alistair Francis, 2024/01/10