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[PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
From: |
Alistair Francis |
Subject: |
[PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion |
Date: |
Wed, 10 Jan 2024 18:57:13 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Expose all profile flags for all CPUs when executing
query-cpu-model-expansion. This will allow callers to quickly determine
if a certain profile is implemented by a given CPU. This includes vendor
CPUs - the fact that they don't have profile user flags doesn't mean
that they don't implement the profile.
After this change it's possible to quickly determine if our stock CPUs
implement the existing rva22u64 profile. Here's a few examples:
$ ./build/qemu-system-riscv64 -S -M virt -display none
-qmp tcp:localhost:1234,server,wait=off
$ ./scripts/qmp/qmp-shell localhost:1234
Welcome to the QMP low-level shell!
Connected to QEMU 8.1.50
- As expected, the 'max' CPU implements the rva22u64 profile.
(QEMU) query-cpu-model-expansion type=full model={"name":"max"}
{"return": {"model":
{"name": "rv64", "props": {... "rva22u64": true, ...}}}}
- rv64 is missing "zba", "zbb", "zbs", "zkt" and "zfhmin":
query-cpu-model-expansion type=full model={"name":"rv64"}
{"return": {"model":
{"name": "rv64", "props": {... "rva22u64": false, ...}}}}
query-cpu-model-expansion type=full model={"name":"rv64",
"props":{"zba":true,"zbb":true,"zbs":true,"zkt":true,"zfhmin":true}}
{"return": {"model":
{"name": "rv64", "props": {... "rva22u64": true, ...}}}}
We have no vendor CPUs that supports rva22u64 (veyron-v1 is the closest
- it is missing just 'zkt').
In short, aside from the 'max' CPU, we have no CPUs that supports
rva22u64 by default.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/riscv-qmp-cmds.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index 35f2b21163..c48b9cfa67 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -115,6 +115,19 @@ static void riscv_obj_add_named_feats_qdict(Object *obj,
QDict *qdict_out)
}
}
+static void riscv_obj_add_profiles_qdict(Object *obj, QDict *qdict_out)
+{
+ RISCVCPUProfile *profile;
+ QObject *value;
+
+ for (int i = 0; riscv_profiles[i] != NULL; i++) {
+ profile = riscv_profiles[i];
+ value = QOBJECT(qbool_from_bool(profile->enabled));
+
+ qdict_put_obj(qdict_out, profile->name, value);
+ }
+}
+
static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props,
const QDict *qdict_in,
Error **errp)
@@ -219,6 +232,7 @@ CpuModelExpansionInfo
*qmp_query_cpu_model_expansion(CpuModelExpansionType type,
riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_exts);
riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts);
riscv_obj_add_named_feats_qdict(obj, qdict_out);
+ riscv_obj_add_profiles_qdict(obj, qdict_out);
/* Add our CPU boolean options too */
riscv_obj_add_qdict_prop(obj, qdict_out, "mmu");
--
2.43.0
- [PULL 34/65] target/riscv/tcg: add 'zic64b' support, (continued)
- [PULL 34/65] target/riscv/tcg: add 'zic64b' support, Alistair Francis, 2024/01/10
- [PULL 35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion, Alistair Francis, 2024/01/10
- [PULL 37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable, Alistair Francis, 2024/01/10
- [PULL 29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU, Alistair Francis, 2024/01/10
- [PULL 36/65] target/riscv: add rva22u64 profile definition, Alistair Francis, 2024/01/10
- [PULL 38/65] target/riscv/tcg: add user flag for profile support, Alistair Francis, 2024/01/10
- [PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits, Alistair Francis, 2024/01/10
- [PULL 39/65] target/riscv/tcg: add MISA user options hash, Alistair Francis, 2024/01/10
- [PULL 42/65] target/riscv/tcg: add hash table insert helpers, Alistair Francis, 2024/01/10
- [PULL 44/65] target/riscv/tcg: validate profiles during finalize, Alistair Francis, 2024/01/10
- [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion,
Alistair Francis <=
- [PULL 46/65] target/riscv: add 'rva22u64' CPU, Alistair Francis, 2024/01/10
- [PULL 47/65] target/riscv: implement svade, Alistair Francis, 2024/01/10
- [PULL 48/65] target/riscv: add priv ver restriction to profiles, Alistair Francis, 2024/01/10
- [PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier, Alistair Francis, 2024/01/10
- [PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit(), Alistair Francis, 2024/01/10
- [PULL 51/65] target/riscv: add satp_mode profile support, Alistair Francis, 2024/01/10
- [PULL 52/65] target/riscv: add 'parent' in profile description, Alistair Francis, 2024/01/10
- [PULL 53/65] target/riscv: add RVA22S64 profile, Alistair Francis, 2024/01/10
- [PULL 54/65] target/riscv: add rva22s64 cpu, Alistair Francis, 2024/01/10
- [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket, Alistair Francis, 2024/01/10