[Qemu-devel] [PATCH v2] tcg: Implement tcg_gen_shri2_i64()

[David Hildenbrand]

Will be helpful for s390x. Input 128 bit and output 64 bit only, which
is sufficient for now.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
---

v1 -> v2:
- Use one output (lower part) only
- Shield off big shifts by an assert

 tcg/tcg-op.c | 15 +++++++++++++++
 tcg/tcg-op.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 1bd7ef24af..e4fa75c074 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2381,6 +2381,21 @@ void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 
al,
     }
 }
 
+void tcg_gen_shri2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, int64_t count)
+{
+    tcg_debug_assert(count >= 0 && count <= 64);
+    if (count == 0) {
+        tcg_gen_mov_i64(ret, al);
+    } else if (count == 64) {
+        tcg_gen_mov_i64(ret, ah);
+    } else {
+        TCGv_i64 t0 = tcg_temp_new_i64();
+        tcg_gen_shri_i64(t0, al, count);
+        tcg_gen_deposit_i64(ret, t0, ah, 64 - count, count);
+        tcg_temp_free_i64(t0);
+    }
+}
+
 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
 {
     if (TCG_TARGET_HAS_mulu2_i64) {
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index d3e51b15af..1ffe689276 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -513,6 +513,7 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
                       TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
                       TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
+void tcg_gen_shri2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, int64_t count);
 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 
arg2);
-- 
2.17.2