Re: [Qemu-devel] [PULL 00/27] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: address@hidden
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
4a5fa28330 gdbstub: Send a reply to the vKill packet.
377a1b0e65 target/arm: Add missing clear_tail calls
f7d3af4abb target/arm: Use vector operations for saturation
df8ca3278b target/arm: Split out FPSCR.QC to a vector field
09d6eda7b5 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
08ed43f236 target/arm: Split out flags setting from vfp compares
13d1fa231c target/arm: Fix arm_cpu_dump_state vs FPSCR
89c3c77cc7 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
9ef6297e49 target/arm: Remove neon min/max helpers
409e13e7c6 target/arm: Use tcg integer min/max primitives for neon
dbcd048d95 target/arm: Use vector minmax expanders for aarch32
35d58be2dc target/arm: Use vector minmax expanders for aarch64
ac2c4a327a target/arm: Rely on optimization within tcg_gen_gvec_or
081212958f hw/arm/armsse: Fix miswiring of expansion IRQs
425d5d76ea hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
1b1ca68043 MAINTAINERS: Remove Peter Crosthwaite from various entries
d313b64e06 arm: Allow system registers for KVM guests to be changed by QEMU code
ad6e481428 linux-user/elfload: enable HWCAP_CPUID for AArch64
ec69944c2a target/arm: expose remaining CPUID registers as RAZ
59b0c47736 target/arm: expose MPIDR_EL1 to userspace
38948116f6 target/arm: expose CPUID registers to userspace
de5c25835f target/arm: relax permission checks for HWCAP_CPUID registers
f2d76c5e1d target/arm: Restructure disas_fp_int_conv
f71a727256 target/arm: Force result size into dp after operation
5a52d23be1 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
b7f2a14413 target/arm: Implement HACR_EL2
eb86b450b4 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

=== OUTPUT BEGIN ===
1/27 Checking commit eb86b450b4d2 (target/arm: Fix CRn to be 14 for 
PMEVTYPER/PMEVCNTR)
2/27 Checking commit b7f2a1441331 (target/arm: Implement HACR_EL2)
3/27 Checking commit 5a52d23be1a7 (target/arm: Fix int128_make128 lo, hi order 
in paired_cmpxchg64_be)
4/27 Checking commit f71a72725699 (target/arm: Force result size into dp after 
operation)
5/27 Checking commit f2d76c5e1d0e (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit de5c25835ff7 (target/arm: relax permission checks for 
HWCAP_CPUID registers)
7/27 Checking commit 38948116f604 (target/arm: expose CPUID registers to 
userspace)
8/27 Checking commit 59b0c4773654 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit ec69944c2adf (target/arm: expose remaining CPUID registers 
as RAZ)
10/27 Checking commit ad6e481428ed (linux-user/elfload: enable HWCAP_CPUID for 
AArch64)
11/27 Checking commit d313b64e0651 (arm: Allow system registers for KVM guests 
to be changed by QEMU code)
12/27 Checking commit 1b1ca680431d (MAINTAINERS: Remove Peter Crosthwaite from 
various entries)
13/27 Checking commit 425d5d76ea60 (hw/intc/armv7m_nvic: Allow byte accesses to 
SHPR1)
14/27 Checking commit 081212958fd9 (hw/arm/armsse: Fix miswiring of expansion 
IRQs)
15/27 Checking commit ac2c4a327a45 (target/arm: Rely on optimization within 
tcg_gen_gvec_or)
16/27 Checking commit 35d58be2dcb7 (target/arm: Use vector minmax expanders for 
aarch64)
17/27 Checking commit dbcd048d9559 (target/arm: Use vector minmax expanders for 
aarch32)
18/27 Checking commit 409e13e7c607 (target/arm: Use tcg integer min/max 
primitives for neon)
19/27 Checking commit 9ef6297e49d3 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 89c3c77cc712 (target/arm: Fix vfp_gdb_get/set_reg vs 
FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+    case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;

ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+    case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;

total: 2 errors, 0 warnings, 16 lines checked

Patch 20/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

21/27 Checking commit 13d1fa231c8e (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 08ed43f236ec (target/arm: Split out flags setting from 
vfp compares)
23/27 Checking commit 09d6eda7b5ab (target/arm: Fix set of bits kept in 
xregs[ARM_VFP_FPSCR])
24/27 Checking commit df8ca3278b2c (target/arm: Split out FPSCR.QC to a vector 
field)
25/27 Checking commit f7d3af4abb72 (target/arm: Use vector operations for 
saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+    TYPEN *d = vd, *n = vn; TYPEM *m = vm;                                 \
                                   ^

total: 1 errors, 0 warnings, 438 lines checked

Patch 25/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

26/27 Checking commit 377a1b0e655a (target/arm: Add missing clear_tail calls)
27/27 Checking commit 4a5fa2833065 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden