Re: [Qemu-devel] [PULL 00/27] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: address@hidden
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
8b28bf8c02 gdbstub: Send a reply to the vKill packet.
35e9a92f59 target/arm: Add missing clear_tail calls
679145406a target/arm: Use vector operations for saturation
a14d6bfaf2 target/arm: Split out FPSCR.QC to a vector field
f8fbccbba5 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
ba0918dc3a target/arm: Split out flags setting from vfp compares
97f0d8db7d target/arm: Fix arm_cpu_dump_state vs FPSCR
fcc5258d65 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
496ebd96d8 target/arm: Remove neon min/max helpers
57606e781d target/arm: Use tcg integer min/max primitives for neon
fb20fb9747 target/arm: Use vector minmax expanders for aarch32
09fe9b2ce9 target/arm: Use vector minmax expanders for aarch64
76ee8fbab5 target/arm: Rely on optimization within tcg_gen_gvec_or
a9bf743839 hw/arm/armsse: Fix miswiring of expansion IRQs
a2989bb924 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
d58f7f8928 MAINTAINERS: Remove Peter Crosthwaite from various entries
0db6bcf0f7 arm: Allow system registers for KVM guests to be changed by QEMU code
cc4082ee0d linux-user/elfload: enable HWCAP_CPUID for AArch64
a317a40397 target/arm: expose remaining CPUID registers as RAZ
50b5ab0dc0 target/arm: expose MPIDR_EL1 to userspace
424e73b993 target/arm: expose CPUID registers to userspace
f8c3d064cd target/arm: relax permission checks for HWCAP_CPUID registers
944dfb207b target/arm: Restructure disas_fp_int_conv
770275cef8 target/arm: Force result size into dp after operation
86975d477f target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
0fad7188ea target/arm: Implement HACR_EL2
df8c887922 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

=== OUTPUT BEGIN ===
1/27 Checking commit df8c88792230 (target/arm: Fix CRn to be 14 for 
PMEVTYPER/PMEVCNTR)
2/27 Checking commit 0fad7188ea17 (target/arm: Implement HACR_EL2)
3/27 Checking commit 86975d477ff0 (target/arm: Fix int128_make128 lo, hi order 
in paired_cmpxchg64_be)
4/27 Checking commit 770275cef89b (target/arm: Force result size into dp after 
operation)
5/27 Checking commit 944dfb207b6b (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit f8c3d064cd92 (target/arm: relax permission checks for 
HWCAP_CPUID registers)
7/27 Checking commit 424e73b99329 (target/arm: expose CPUID registers to 
userspace)
8/27 Checking commit 50b5ab0dc071 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit a317a4039735 (target/arm: expose remaining CPUID registers 
as RAZ)
10/27 Checking commit cc4082ee0d10 (linux-user/elfload: enable HWCAP_CPUID for 
AArch64)
11/27 Checking commit 0db6bcf0f7ac (arm: Allow system registers for KVM guests 
to be changed by QEMU code)
12/27 Checking commit d58f7f89287b (MAINTAINERS: Remove Peter Crosthwaite from 
various entries)
13/27 Checking commit a2989bb92474 (hw/intc/armv7m_nvic: Allow byte accesses to 
SHPR1)
14/27 Checking commit a9bf743839e7 (hw/arm/armsse: Fix miswiring of expansion 
IRQs)
15/27 Checking commit 76ee8fbab5cf (target/arm: Rely on optimization within 
tcg_gen_gvec_or)
16/27 Checking commit 09fe9b2ce988 (target/arm: Use vector minmax expanders for 
aarch64)
17/27 Checking commit fb20fb9747a0 (target/arm: Use vector minmax expanders for 
aarch32)
18/27 Checking commit 57606e781d78 (target/arm: Use tcg integer min/max 
primitives for neon)
19/27 Checking commit 496ebd96d8f5 (target/arm: Remove neon min/max helpers)
20/27 Checking commit fcc5258d65aa (target/arm: Fix vfp_gdb_get/set_reg vs 
FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+    case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;

ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+    case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;

total: 2 errors, 0 warnings, 16 lines checked

Patch 20/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

21/27 Checking commit 97f0d8db7d84 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit ba0918dc3a40 (target/arm: Split out flags setting from 
vfp compares)
23/27 Checking commit f8fbccbba569 (target/arm: Fix set of bits kept in 
xregs[ARM_VFP_FPSCR])
24/27 Checking commit a14d6bfaf27b (target/arm: Split out FPSCR.QC to a vector 
field)
25/27 Checking commit 679145406ae5 (target/arm: Use vector operations for 
saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+    TYPEN *d = vd, *n = vn; TYPEM *m = vm;                                 \
                                   ^

total: 1 errors, 0 warnings, 438 lines checked

Patch 25/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

26/27 Checking commit 35e9a92f5916 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 8b28bf8c02b6 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
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