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[Qemu-devel] [PULL 21/24] target/hppa: Rearrange log conditions
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 21/24] target/hppa: Rearrange log conditions |
Date: |
Mon, 11 Feb 2019 20:57:18 -0800 |
We will be fixing do_cond vs signed overflow, which requires
that do_log_cond not rely on do_cond.
Signed-off-by: Richard Henderson <address@hidden>
---
target/hppa/translate.c | 56 +++++++++++++++++++++++++++++++++++------
1 file changed, 49 insertions(+), 7 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 6836fb6245..aae5714235 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -432,6 +432,15 @@ static DisasCond cond_make_f(void)
};
}
+static DisasCond cond_make_t(void)
+{
+ return (DisasCond){
+ .c = TCG_COND_ALWAYS,
+ .a0 = NULL,
+ .a1 = NULL,
+ };
+}
+
static DisasCond cond_make_n(void)
{
return (DisasCond){
@@ -930,17 +939,50 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
return cond;
}
-/* Similar, but for logicals, where the carry and overflow bits are not
- computed, and use of them is undefined. */
+/*
+ * Similar, but for logicals, where the carry and overflow bits are not
+ * computed, and use of them is undefined.
+ *
+ * Undefined or not, hardware does not trap. It seems reasonable to
+ * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
+ * how cases c={2,3} are treated.
+ */
static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
{
- switch (cf >> 1) {
- case 4: case 5: case 6:
- cf &= 1;
- break;
+ switch (cf) {
+ case 0: /* never */
+ case 9: /* undef, C */
+ case 11: /* undef, C & !Z */
+ case 12: /* undef, V */
+ return cond_make_f();
+
+ case 1: /* true */
+ case 8: /* undef, !C */
+ case 10: /* undef, !C | Z */
+ case 13: /* undef, !V */
+ return cond_make_t();
+
+ case 2: /* == */
+ return cond_make_0(TCG_COND_EQ, res);
+ case 3: /* <> */
+ return cond_make_0(TCG_COND_NE, res);
+ case 4: /* < */
+ return cond_make_0(TCG_COND_LT, res);
+ case 5: /* >= */
+ return cond_make_0(TCG_COND_GE, res);
+ case 6: /* <= */
+ return cond_make_0(TCG_COND_LE, res);
+ case 7: /* > */
+ return cond_make_0(TCG_COND_GT, res);
+
+ case 14: /* OD */
+ case 15: /* EV */
+ return do_cond(cf, res, NULL, NULL);
+
+ default:
+ g_assert_not_reached();
}
- return do_cond(cf, res, res, res);
}
/* Similar, but for shift/extract/deposit conditions. */
--
2.17.2
- [Qemu-devel] [PULL 00/24] target/hppa patch queue, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 02/24] target/hppa: Begin using scripts/decodetree.py, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 07/24] target/hppa: Convert arithmetic/logical insns, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 09/24] target/hppa: Convert fp multiply-add, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 21/24] target/hppa: Rearrange log conditions,
Richard Henderson <=
- [Qemu-devel] [PULL 03/24] target/hppa: Convert move to/from system registers, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 04/24] target/hppa: Convert remainder of system insns, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 06/24] target/hppa: Convert memory management insns, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 19/24] target/hppa: Merge translate_one into hppa_tr_translate_insn, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 20/24] target/hppa: move GETPC to HELPER() functions, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 05/24] target/hppa: Unify specializations of OR, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 23/24] target/hppa: fix dcor instruction, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 16/24] target/hppa: Convert halt/reset insns, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 15/24] target/hppa: Convert fp indexed memory insns, Richard Henderson, 2019/02/11
- [Qemu-devel] [PULL 24/24] hw/hppa: forward requests to CPU HPA, Richard Henderson, 2019/02/11