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Re: [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel to vector opera
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel to vector operations |
Date: |
Wed, 19 Dec 2018 17:35:58 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Dec 17, 2018 at 10:39:02PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <address@hidden>
Acked-by: David Gibson <address@hidden>
> ---
> target/ppc/translate/vsx-impl.inc.c | 55 ++++++++++++++---------------
> 1 file changed, 27 insertions(+), 28 deletions(-)
>
> diff --git a/target/ppc/translate/vsx-impl.inc.c
> b/target/ppc/translate/vsx-impl.inc.c
> index a040038ed4..dc32471cd7 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1280,40 +1280,39 @@ static void glue(gen_, name)(DisasContext * ctx)
> \
> VSX_XXMRG(xxmrghw, 1)
> VSX_XXMRG(xxmrglw, 0)
>
> +static void xxsel_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c)
> +{
> + tcg_gen_and_i64(b, b, c);
> + tcg_gen_andc_i64(a, a, c);
> + tcg_gen_or_i64(t, a, b);
> +}
> +
> +static void xxsel_vec(unsigned vece, TCGv_vec t, TCGv_vec a,
> + TCGv_vec b, TCGv_vec c)
> +{
> + tcg_gen_and_vec(vece, b, b, c);
> + tcg_gen_andc_vec(vece, a, a, c);
> + tcg_gen_or_vec(vece, t, a, b);
> +}
> +
> static void gen_xxsel(DisasContext * ctx)
> {
> - TCGv_i64 a, b, c, tmp;
> + static const GVecGen4 g = {
> + .fni8 = xxsel_i64,
> + .fniv = xxsel_vec,
> + .vece = MO_64,
> + };
> + int rt = xT(ctx->opcode);
> + int ra = xA(ctx->opcode);
> + int rb = xB(ctx->opcode);
> + int rc = xC(ctx->opcode);
> +
> if (unlikely(!ctx->vsx_enabled)) {
> gen_exception(ctx, POWERPC_EXCP_VSXU);
> return;
> }
> - a = tcg_temp_new_i64();
> - b = tcg_temp_new_i64();
> - c = tcg_temp_new_i64();
> - tmp = tcg_temp_new_i64();
> -
> - get_cpu_vsrh(a, xA(ctx->opcode));
> - get_cpu_vsrh(b, xB(ctx->opcode));
> - get_cpu_vsrh(c, xC(ctx->opcode));
> -
> - tcg_gen_and_i64(b, b, c);
> - tcg_gen_andc_i64(a, a, c);
> - tcg_gen_or_i64(tmp, a, b);
> - set_cpu_vsrh(xT(ctx->opcode), tmp);
> -
> - get_cpu_vsrl(a, xA(ctx->opcode));
> - get_cpu_vsrl(b, xB(ctx->opcode));
> - get_cpu_vsrl(c, xC(ctx->opcode));
> -
> - tcg_gen_and_i64(b, b, c);
> - tcg_gen_andc_i64(a, a, c);
> - tcg_gen_or_i64(tmp, a, b);
> - set_cpu_vsrl(xT(ctx->opcode), tmp);
> -
> - tcg_temp_free_i64(a);
> - tcg_temp_free_i64(b);
> - tcg_temp_free_i64(c);
> - tcg_temp_free_i64(tmp);
> + tcg_gen_gvec_4(vsr_full_offset(rt), vsr_full_offset(ra),
> + vsr_full_offset(rb), vsr_full_offset(rc), 16, 16, &g);
> }
>
> static void gen_xxspltw(DisasContext *ctx)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-devel] [PATCH 19/34] target/ppc: convert vspltis[bhw] to use vector operations, (continued)
- [Qemu-devel] [PATCH 20/34] target/ppc: convert vsplt[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 16/34] target/ppc: move FP and VMX registers into aligned vsr register array, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 24/34] target/ppc: convert xxspltw to vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 11/34] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel to vector operations, Richard Henderson, 2018/12/18
- Re: [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel to vector operations,
David Gibson <=
- [Qemu-devel] [PATCH 01/34] tcg: Add logical simplifications during gvec expand, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 13/34] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR register access, Richard Henderson, 2018/12/18
- Re: [Qemu-devel] [PATCH 00/34] tcg, target/ppc vector improvements, Mark Cave-Ayland, 2018/12/18
- Re: [Qemu-devel] [PATCH 00/34] tcg, target/ppc vector improvements, Mark Cave-Ayland, 2018/12/18