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Re: [Qemu-devel] [PATCH 24/34] target/ppc: convert xxspltw to vector ope
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 24/34] target/ppc: convert xxspltw to vector operations |
Date: |
Wed, 19 Dec 2018 17:35:14 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Dec 17, 2018 at 10:39:01PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <address@hidden>
Acked-by: David Gibson <address@hidden>
> ---
> target/ppc/translate/vsx-impl.inc.c | 36 +++++++++--------------------
> 1 file changed, 11 insertions(+), 25 deletions(-)
>
> diff --git a/target/ppc/translate/vsx-impl.inc.c
> b/target/ppc/translate/vsx-impl.inc.c
> index d88d6bbd74..a040038ed4 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1318,38 +1318,24 @@ static void gen_xxsel(DisasContext * ctx)
>
> static void gen_xxspltw(DisasContext *ctx)
> {
> - TCGv_i64 b, b2;
> - TCGv_i64 vsr;
> -
> - vsr = tcg_temp_new_i64();
> - if (UIM(ctx->opcode) & 2) {
> - get_cpu_vsrl(vsr, xB(ctx->opcode));
> - } else {
> - get_cpu_vsrh(vsr, xB(ctx->opcode));
> - }
> + int rt = xT(ctx->opcode);
> + int rb = xB(ctx->opcode);
> + int uim = UIM(ctx->opcode);
> + int tofs, bofs;
>
> if (unlikely(!ctx->vsx_enabled)) {
> gen_exception(ctx, POWERPC_EXCP_VSXU);
> return;
> }
>
> - b = tcg_temp_new_i64();
> - b2 = tcg_temp_new_i64();
> + tofs = vsr_full_offset(rt);
> + bofs = vsr_full_offset(rb);
> + bofs += uim << MO_32;
> +#ifndef HOST_WORDS_BIG_ENDIAN
> + bofs ^= 8 | 4;
> +#endif
>
> - if (UIM(ctx->opcode) & 1) {
> - tcg_gen_ext32u_i64(b, vsr);
> - } else {
> - tcg_gen_shri_i64(b, vsr, 32);
> - }
> -
> - tcg_gen_shli_i64(b2, b, 32);
> - tcg_gen_or_i64(vsr, b, b2);
> - set_cpu_vsrh(xT(ctx->opcode), vsr);
> - set_cpu_vsrl(xT(ctx->opcode), vsr);
> -
> - tcg_temp_free_i64(vsr);
> - tcg_temp_free_i64(b);
> - tcg_temp_free_i64(b2);
> + tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
> }
>
> #define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-devel] [PATCH 33/34] target/ppc: convert vadd*s and vsub*s to vector operations, (continued)
- [Qemu-devel] [PATCH 23/34] target/ppc: convert xxspltib to vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 19/34] target/ppc: convert vspltis[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 20/34] target/ppc: convert vsplt[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 16/34] target/ppc: move FP and VMX registers into aligned vsr register array, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 24/34] target/ppc: convert xxspltw to vector operations, Richard Henderson, 2018/12/18
- Re: [Qemu-devel] [PATCH 24/34] target/ppc: convert xxspltw to vector operations,
David Gibson <=
- [Qemu-devel] [PATCH 11/34] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel to vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 01/34] tcg: Add logical simplifications during gvec expand, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 13/34] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR register access, Richard Henderson, 2018/12/18