[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5 |
Date: |
Thu, 13 Dec 2018 14:54:38 +0000 |
From: Richard Henderson <address@hidden>
Post v8.4 bits taken from SysReg_v85_xml-00bet8.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 79d58978f7c..20d97b66def 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1302,6 +1302,16 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define SCR_ST (1U << 11)
#define SCR_TWI (1U << 12)
#define SCR_TWE (1U << 13)
+#define SCR_TLOR (1U << 14)
+#define SCR_TERR (1U << 15)
+#define SCR_APK (1U << 16)
+#define SCR_API (1U << 17)
+#define SCR_EEL2 (1U << 18)
+#define SCR_EASE (1U << 19)
+#define SCR_NMEA (1U << 20)
+#define SCR_FIEN (1U << 21)
+#define SCR_ENSCXT (1U << 25)
+#define SCR_ATA (1U << 26)
#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
--
2.19.2
- [Qemu-devel] [PULL 01/37] hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link(), (continued)
- [Qemu-devel] [PULL 01/37] hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link(), Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 02/37] Allow AArch64 processors to boot from a kernel placed over 4GB, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 06/37] core/empty_slot: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 10/37] milkymist-softusb: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 09/37] gpio/puv3_gpio: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 12/37] intc/puv3_intc: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 13/37] milkymist-hpdmc: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 11/37] input/pl050: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 31/37] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5,
Peter Maydell <=
- [Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD extension, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 37/37] target/arm: Implement the ARMv8.1-LOR extension, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 34/37] target/arm: Implement the ARMv8.2-AA32HPD extension, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 36/37] target/arm: Use arm_hcr_el2_eff more places, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 35/37] target/arm: Introduce arm_hcr_el2_eff, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 29/37] target/arm: Add HCR_EL2 bits up to ARMv8.5, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 27/37] hw/arm: versal: Correct the nr of IRQs to 192, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 28/37] target/arm: Move id_aa64mmfr* to ARMISARegisters, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 26/37] hw/arm: versal: Use IRQs 111 - 118 for virtio-mmio, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 25/37] hw/arm: versal: Reduce number of virtio-mmio instances, Peter Maydell, 2018/12/13