[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write |
Date: |
Thu, 13 Dec 2018 14:54:40 +0000 |
From: Richard Henderson <address@hidden>
Because EL3 has a fixed execution mode, we can properly decide
which of the bits are RES{0,1}.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 2 --
target/arm/helper.c | 14 +++++++++-----
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 20d97b66def..b8dbdb5e014 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1312,8 +1312,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define SCR_FIEN (1U << 21)
#define SCR_ENSCXT (1U << 25)
#define SCR_ATA (1U << 26)
-#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
-#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bf020364e1d..1dad277804f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1279,11 +1279,15 @@ static void vbar_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
- /* We only mask off bits that are RES0 both for AArch64 and AArch32.
- * For bits that vary between AArch32/64, code needs to check the
- * current execution mode before directly using the feature bit.
- */
- uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
+ /* Begin with base v8.0 state. */
+ uint32_t valid_mask = 0x3fff;
+
+ if (arm_el_is_aa64(env, 3)) {
+ value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
+ valid_mask &= ~SCR_NET;
+ } else {
+ valid_mask &= ~(SCR_RW | SCR_ST);
+ }
if (!arm_feature(env, ARM_FEATURE_EL2)) {
valid_mask &= ~SCR_HCE;
--
2.19.2
- [Qemu-devel] [PULL 07/37] display/g364fb: Convert sysbus init function to realize function, (continued)
- [Qemu-devel] [PULL 07/37] display/g364fb: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 08/37] dma/puv3_dma: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 01/37] hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link(), Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 02/37] Allow AArch64 processors to boot from a kernel placed over 4GB, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 06/37] core/empty_slot: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 10/37] milkymist-softusb: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 09/37] gpio/puv3_gpio: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 12/37] intc/puv3_intc: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 13/37] milkymist-hpdmc: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 11/37] input/pl050: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write,
Peter Maydell <=
- [Qemu-devel] [PULL 31/37] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD extension, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 37/37] target/arm: Implement the ARMv8.1-LOR extension, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 34/37] target/arm: Implement the ARMv8.2-AA32HPD extension, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 36/37] target/arm: Use arm_hcr_el2_eff more places, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 35/37] target/arm: Introduce arm_hcr_el2_eff, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 29/37] target/arm: Add HCR_EL2 bits up to ARMv8.5, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 27/37] hw/arm: versal: Correct the nr of IRQs to 192, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 28/37] target/arm: Move id_aa64mmfr* to ARMISARegisters, Peter Maydell, 2018/12/13