Re: [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND

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Re: [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND

From:	Richard Henderson
Subject:	Re: [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
Date:	Wed, 31 Oct 2018 22:27:51 +0000
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1

On 10/31/18 8:44 PM, Alistair Francis wrote:
> This series causes a lot of kernel oops during boot...

The only bug I can see is in trans_addw.  But that's a biggie and could easily
explain, since non-extended values could have caused a compare to misfire.


r~

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Re: [Qemu-devel] [PATCH v3 07/35] target/riscv: Convert RVXI fence insns to decodetree, (continued)
- [Qemu-devel] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-devel] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree, Richard Henderson, 2018/10/31
- [Qemu-devel] [PATCH v3 15/35] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 08/35] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-devel] [PATCH v3 08/35] target/riscv: Convert RVXI csr insns to decodetree, Alistair, 2018/10/31
- [Qemu-devel] [PATCH v3 20/35] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-devel] [PATCH v3 20/35] target/riscv: Remove gen_jalr(), Alistair, 2018/10/31
- [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Alistair Francis, 2018/10/31
    - Re: [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Richard Henderson <=
  - Re: [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Richard Henderson, 2018/10/31
- [Qemu-devel] [PATCH v3 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-devel] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Richard Henderson, 2018/10/31
- [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding, Richard Henderson, 2018/10/31
- [Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-devel] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Richard Henderson, 2018/10/31

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