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[Qemu-devel] [PATCH v6 04/18] target/mips: Add and integrate MXU decodin
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v6 04/18] target/mips: Add and integrate MXU decoding engine placeholder |
Date: |
Tue, 23 Oct 2018 18:18:15 +0200 |
From: Aleksandar Markovic <address@hidden>
Provide the placeholder and add the invocation logic for MXU
decoding engine.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fefe9ac..128cabe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23844,6 +23844,12 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
}
}
+static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
+{
+ MIPS_INVAL("decode_opc_mxu");
+ generate_exception_end(ctx, EXCP_RI);
+}
+
static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd;
@@ -26087,6 +26093,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
case OPC_SPECIAL2:
if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
decode_tx79_mmi(env, ctx);
+ } else if (ctx->insn_flags & ASE_MXU) {
+ decode_opc_mxu(env, ctx);
} else {
decode_opc_special2_legacy(env, ctx);
}
--
2.7.4
- [Qemu-devel] [PATCH v6 00/18] target/mips: Add limited support for Ingenic's MXU ASE, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 01/18] target/mips: Introduce MXU registers, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 02/18] target/mips: Define a bit for MXU in insn_flags, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 04/18] target/mips: Add and integrate MXU decoding engine placeholder,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v6 03/18] target/mips: Amend MXU instruction opcodes, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 05/18] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 06/18] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 07/18] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 08/18] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 09/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 10/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 11/18] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 13/18] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 12/18] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/23