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[Qemu-devel] [PATCH v6 02/18] target/mips: Define a bit for MXU in insn_
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v6 02/18] target/mips: Define a bit for MXU in insn_flags |
Date: |
Tue, 23 Oct 2018 18:18:13 +0200 |
From: Craig Janeczek <address@hidden>
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/mips-defs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 5177618..dbdb4b2 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -69,6 +69,7 @@
* bits 56-63: vendor-specific ASEs
*/
#define ASE_MMI 0x0100000000000000ULL
+#define ASE_MXU 0x0200000000000000ULL
/* MIPS CPU defines. */
#define CPU_MIPS1 (ISA_MIPS1)
--
2.7.4
- [Qemu-devel] [PATCH v6 00/18] target/mips: Add limited support for Ingenic's MXU ASE, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 01/18] target/mips: Introduce MXU registers, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 02/18] target/mips: Define a bit for MXU in insn_flags,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v6 04/18] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 03/18] target/mips: Amend MXU instruction opcodes, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 05/18] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 06/18] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 07/18] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 08/18] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 09/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 10/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 11/18] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 13/18] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch, Aleksandar Markovic, 2018/10/23