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Re: [Qemu-devel] [PATCH v3 03/10] target/arm: Convert v8 extensions from
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v3 03/10] target/arm: Convert v8 extensions from feature bits to isar tests |
Date: |
Tue, 16 Oct 2018 09:06:57 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 10/16/18 3:40 AM, Peter Maydell wrote:
> On 8 October 2018 at 22:21, Richard Henderson
> <address@hidden> wrote:
>> Most of the v8 extensions are self-contained within the ISAR
>> registers and are not implied by other feature bits, which
>> makes them the easiest to convert.
>>
>> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
>> Signed-off-by: Richard Henderson <address@hidden>
>
>> diff --git a/target/arm/translate.h b/target/arm/translate.h
>> index c1b65f3efb..1d60569583 100644
>> --- a/target/arm/translate.h
>> +++ b/target/arm/translate.h
>> @@ -7,6 +7,7 @@
>> /* internal defines */
>> typedef struct DisasContext {
>> DisasContextBase base;
>> + ARMCPU *cpu; /* for access to the id_* registers */
>
> The translate code is not supposed to have access to either ARMCPU
> or the ARMCPUState env pointer. Putting a pointer to cpu into the
> DisasContext defeats this. This is why aarch64_tr_init_disas_context()
> and the 32-bit equivalent extract all the info they need from
> arm_cpu and env and put it into DisasContext fields.
I know that.
I also know that if we don't do it this way, then we need to duplicate all of
the routines that query the ID registers. I think this way is cleaner.
We simply have to be vigilant about how ctx->cpu is used otherwise.
r~
- [Qemu-devel] [PATCH v3 01/10] target/arm: Fix aarch64_sve_change_el wrt EL0, (continued)
- [Qemu-devel] [PATCH v3 01/10] target/arm: Fix aarch64_sve_change_el wrt EL0, Richard Henderson, 2018/10/08
- [Qemu-devel] [PATCH v3 09/10] target/arm: Convert sve from feature bit to aa64pfr0 test, Richard Henderson, 2018/10/08
- [Qemu-devel] [PATCH v3 06/10] target/arm: Convert division from feature bits to isar0 tests, Richard Henderson, 2018/10/08
- [Qemu-devel] [PATCH v3 05/10] target/arm: Fix cortex-a7 id_isar0, Richard Henderson, 2018/10/08
- [Qemu-devel] [PATCH v3 04/10] target/arm: Align cortex-r5 id_isar0, Richard Henderson, 2018/10/08
- [Qemu-devel] [PATCH v3 02/10] target/arm: Define fields of ISAR registers, Richard Henderson, 2018/10/08
- [Qemu-devel] [PATCH v3 07/10] target/arm: Convert jazelle from feature bit to isar1 test, Richard Henderson, 2018/10/08
- [Qemu-devel] [PATCH v3 03/10] target/arm: Convert v8 extensions from feature bits to isar tests, Richard Henderson, 2018/10/08
- Re: [Qemu-devel] [PATCH v3 00/10] target/arm: Rely on id regs instead of features, Peter Maydell, 2018/10/16