Re: [Qemu-devel] [PATCH v5 18/28] target/mips: Add availability control for DSP R3 ASE

[Philippe Mathieu-Daudé]

On Fri, Oct 12, 2018 at 6:52 PM Aleksandar Markovic
<address@hidden> wrote:
>
> From: Stefan Markovic <address@hidden>
>
> Add infrastructure for availability control for DSP R3 ASE MIPS
> instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
> this is likely to be changed in near future.
>
> Reviewed-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>

> ---
>  target/mips/internal.h           | 11 ++++++++---
>  target/mips/translate.c          | 13 ++++++++++++-
>  target/mips/translate_init.inc.c |  3 ++-
>  3 files changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/target/mips/internal.h b/target/mips/internal.h
> index 54bf39f..e367d7e 100644
> --- a/target/mips/internal.h
> +++ b/target/mips/internal.h
> @@ -310,8 +310,8 @@ static inline void compute_hflags(CPUMIPSState *env)
>      env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
>                       MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
>                       MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
> -                     MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
> -                     MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
> +                     MIPS_HFLAG_DSPR3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
> +                     MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
>      if (env->CP0_Status & (1 << CP0St_ERL)) {
>          env->hflags |= MIPS_HFLAG_ERL;
>      }
> @@ -358,7 +358,12 @@ static inline void compute_hflags(CPUMIPSState *env)
>          (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
>          env->hflags |= MIPS_HFLAG_SBRI;
>      }
> -    if (env->insn_flags & ASE_DSPR2) {
> +    if (env->insn_flags & ASE_DSPR3) {
> +        if (env->CP0_Status & (1 << CP0St_MX)) {
> +            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
> +                           MIPS_HFLAG_DSPR3;
> +        }
> +    } else if (env->insn_flags & ASE_DSPR2) {
>          /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
>             so enable to access DSPR2 resources. */
>          if (env->CP0_Status & (1 << CP0St_MX)) {
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e9c3a14..c3ad65c 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1869,6 +1869,17 @@ static inline void check_dspr2(DisasContext *ctx)
>      }
>  }
>
> +static inline void check_dspr3(DisasContext *ctx)
> +{
> +    if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) {
> +        if (ctx->insn_flags & ASE_DSP) {
> +            generate_exception_end(ctx, EXCP_DSPDIS);
> +        } else {
> +            generate_exception_end(ctx, EXCP_RI);
> +        }
> +    }
> +}
> +
>  /* This code generates a "reserved instruction" exception if the
>     CPU does not support the instruction set corresponding to flags. */
>  static inline void check_insn(DisasContext *ctx, int flags)
> @@ -20285,7 +20296,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState 
> *env, DisasContext *ctx)
>                      gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
>                      break;
>                  case NM_BPOSGE32C:
> -                    check_dspr2(ctx);
> +                    check_dspr3(ctx);
>                      {
>                          int32_t imm = extract32(ctx->opcode, 1, 13) |
>                                        extract32(ctx->opcode, 0, 1) << 13;
> diff --git a/target/mips/translate_init.inc.c 
> b/target/mips/translate_init.inc.c
> index b3320b9..d7cd4ee 100644
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -485,7 +485,8 @@ const mips_def_t mips_defs[] =
>          .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
>          .SEGBITS = 32,
>          .PABITS = 32,
> -        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,
> +        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
> +                      ASE_MT,
>          .mmu_type = MMU_TYPE_R4000,
>      },
>  #if defined(TARGET_MIPS64)
> --
> 2.7.4
>
>