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[Qemu-devel] [PATCH v5 12/28] target/mips: Add reset state for PWSize an
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v5 12/28] target/mips: Add reset state for PWSize and PWField registers |
Date: |
Fri, 12 Oct 2018 18:39:20 +0200 |
From: Yongbok Kim <address@hidden>
Add reset state for PWSize and PWField registers. The reset state
is different for pre-R6 and R6 (and post-R6) ISAa.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f669d48..5e508d5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25890,6 +25890,24 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Status |= (1 << CP0St_FR);
}
+ if (env->insn_flags & ISA_MIPS32R6) {
+ /* PTW = 1 */
+ env->CP0_PWSize = 0x40;
+ /* GDI = 12 */
+ /* UDI = 12 */
+ /* MDI = 12 */
+ /* PRI = 12 */
+ /* PTEI = 2 */
+ env->CP0_PWField = 0x0C30C302;
+ } else {
+ /* GDI = 0 */
+ /* UDI = 0 */
+ /* MDI = 0 */
+ /* PRI = 0 */
+ /* PTEI = 2 */
+ env->CP0_PWField = 0x02;
+ }
+
if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
/* microMIPS on reset when Config3.ISA is 3 */
env->hflags |= MIPS_HFLAG_M16;
--
2.7.4
- [Qemu-devel] [PATCH v5 02/28] elf: Add MIPS_ABI_FP_XXX constants, (continued)
- [Qemu-devel] [PATCH v5 02/28] elf: Add MIPS_ABI_FP_XXX constants, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 05/28] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 06/28] linux-user: Add fields that correspond to kernel arch_elf_state, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 07/28] linux-user: Add the field for kernel thread info flags, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 08/28] target/mips: Add CPO PWBase register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 09/28] target/mips: Add CPO PWField register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 10/28] target/mips: Add CPO PWSize register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 11/28] target/mips: Add CPO PWCtl register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 12/28] target/mips: Add reset state for PWSize and PWField registers,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 13/28] target/mips: Implement hardware page table walker, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 17/28] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 20/28] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 16/28] target/mips: Add CP0 SAARI and SAAR registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 15/28] target/mips: Add CPO MemoryMapID register, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 18/28] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 14/28] target/mips: Extend WatchHi registers, Aleksandar Markovic, 2018/10/12
- [Qemu-devel] [PATCH v5 22/28] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/12