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[Qemu-devel] [PATCH v4 16/22] target/mips: Add opcodes for nanoMIPS EVA
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v4 16/22] target/mips: Add opcodes for nanoMIPS EVA instructions |
Date: |
Thu, 11 Oct 2018 13:22:21 +0200 |
From: Dimitrije Nikolic <address@hidden>
Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
Signed-off-by: Dimitrije Nikolic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 34c20fc..f77becb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16686,6 +16686,40 @@ enum {
NM_P_SC = 0x0b,
};
+/* P.LS.E0 instruction pool */
+enum {
+ NM_LBE = 0x00,
+ NM_SBE = 0x01,
+ NM_LBUE = 0x02,
+ NM_P_PREFE = 0x03,
+ NM_LHE = 0x04,
+ NM_SHE = 0x05,
+ NM_LHUE = 0x06,
+ NM_CACHEE = 0x07,
+ NM_LWE = 0x08,
+ NM_SWE = 0x09,
+ NM_P_LLE = 0x0a,
+ NM_P_SCE = 0x0b,
+};
+
+/* P.PREFE instruction pool */
+enum {
+ NM_SYNCIE = 0x00,
+ NM_PREFE = 0x01,
+};
+
+/* P.LLE instruction pool */
+enum {
+ NM_LLE = 0x00,
+ NM_LLWPE = 0x01,
+};
+
+/* P.SCE instruction pool */
+enum {
+ NM_SCE = 0x00,
+ NM_SCWPE = 0x01,
+};
+
/* P.LS.WM instruction pool */
enum {
NM_LWM = 0x00,
--
2.7.4
- [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register, (continued)
- [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 11/22] target/mips: Add CP0 SAARI and SAAR registers, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 13/22] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 15/22] target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S>, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 16/22] target/mips: Add opcodes for nanoMIPS EVA instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v4 18/22] hw/mips: Update ITU to utilise SAARI/SAAR registers, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 19/22] hw/mips: Add Data Scratch Pad RAM, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 20/22] target/mips: Add DEC feature to mips32r6-generic CPU, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 21/22] target/mips: Add MSA ASE to MIPS64R2-generic CPU, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 22/22] target/mips: Add I6500 core configuration, Aleksandar Markovic, 2018/10/11
- Re: [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018, Aleksandar Markovic, 2018/10/12