[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v13 21/24] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_c
From: |
Jinjie Ruan |
Subject: |
[PATCH v13 21/24] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() |
Date: |
Sun, 7 Apr 2024 08:17:30 +0000 |
In CPU Interface, if the IRQ has the non-maskable property, report NMI to
the corresponding PE.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
v12:
- Add Reviewed-by.
v10:
- superprio -> nmi.
- Update the commit message, superpriority -> non-maskable.
v6:
- Add Reviewed-by.
v4:
- Swap the ordering of the IFs.
v3:
- Remove handling nmi_is_irq flag.
---
hw/intc/arm_gicv3_cpuif.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index dff88c4283..60e2d9ec9c 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -1037,6 +1037,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
/* Tell the CPU about its highest priority pending interrupt */
int irqlevel = 0;
int fiqlevel = 0;
+ int nmilevel = 0;
ARMCPU *cpu = ARM_CPU(cs->cpu);
CPUARMState *env = &cpu->env;
@@ -1075,6 +1076,8 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
if (isfiq) {
fiqlevel = 1;
+ } else if (cs->hppi.nmi) {
+ nmilevel = 1;
} else {
irqlevel = 1;
}
@@ -1084,6 +1087,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
qemu_set_irq(cs->parent_fiq, fiqlevel);
qemu_set_irq(cs->parent_irq, irqlevel);
+ qemu_set_irq(cs->parent_nmi, nmilevel);
}
static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
--
2.34.1
- [PATCH v13 08/24] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, (continued)
- [PATCH v13 08/24] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, Jinjie Ruan, 2024/04/07
- [PATCH v13 07/24] target/arm: Add support for NMI in arm_phys_excp_target_el(), Jinjie Ruan, 2024/04/07
- [PATCH v13 06/24] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/04/07
- [PATCH v13 09/24] target/arm: Handle PSTATE.ALLINT on taking an exception, Jinjie Ruan, 2024/04/07
- [PATCH v13 10/24] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/04/07
- [PATCH v13 13/24] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, Jinjie Ruan, 2024/04/07
- [PATCH v13 14/24] hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3, Jinjie Ruan, 2024/04/07
- [PATCH v13 22/24] hw/intc/arm_gicv3: Report the VINMI interrupt, Jinjie Ruan, 2024/04/07
- [PATCH v13 20/24] hw/intc/arm_gicv3: Implement NMI interrupt priority, Jinjie Ruan, 2024/04/07
- [PATCH v13 11/24] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Jinjie Ruan, 2024/04/07
- [PATCH v13 21/24] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(),
Jinjie Ruan <=
- [PATCH v13 15/24] hw/intc/arm_gicv3: Add irq non-maskable property, Jinjie Ruan, 2024/04/07
- [PATCH v13 12/24] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/04/07
- [PATCH v13 23/24] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/04/07
- [PATCH v13 16/24] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/04/07
- [PATCH v13 18/24] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/04/07
- [PATCH v13 17/24] hw/intc/arm_gicv3: Implement GICD_INMIR, Jinjie Ruan, 2024/04/07
- [PATCH v13 19/24] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Jinjie Ruan, 2024/04/07
- [PATCH v13 24/24] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC, Jinjie Ruan, 2024/04/07
- Re: [PATCH v13 00/24] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI, Jinjie Ruan, 2024/04/10