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[PATCH v13 22/24] hw/intc/arm_gicv3: Report the VINMI interrupt
From: |
Jinjie Ruan |
Subject: |
[PATCH v13 22/24] hw/intc/arm_gicv3: Report the VINMI interrupt |
Date: |
Sun, 7 Apr 2024 08:17:31 +0000 |
In vCPU Interface, if the vIRQ has the non-maskable property, report
vINMI to the corresponding vPE.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
v12:
- Do not check nmi_support repetitively.
- Add Reviewed-by.
v10:
- Update the commit message, superpriority -> non-maskable.
v9:
- Update the commit subject and message, vNMI -> vINMI.
v6:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_cpuif.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 60e2d9ec9c..0de7c41f96 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -480,6 +480,7 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
int idx;
int irqlevel = 0;
int fiqlevel = 0;
+ int nmilevel = 0;
idx = hppvi_index(cs);
trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx,
@@ -497,9 +498,17 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
uint64_t lr = cs->ich_lr_el2[idx];
if (icv_hppi_can_preempt(cs, lr)) {
- /* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */
+ /*
+ * Virtual interrupts are simple: G0 are always FIQ, and G1 are
+ * IRQ or NMI which depends on the ICH_LR<n>_EL2.NMI to have
+ * non-maskable property.
+ */
if (lr & ICH_LR_EL2_GROUP) {
- irqlevel = 1;
+ if (lr & ICH_LR_EL2_NMI) {
+ nmilevel = 1;
+ } else {
+ irqlevel = 1;
+ }
} else {
fiqlevel = 1;
}
@@ -509,6 +518,7 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
irqlevel);
qemu_set_irq(cs->parent_vfiq, fiqlevel);
qemu_set_irq(cs->parent_virq, irqlevel);
+ qemu_set_irq(cs->parent_vnmi, nmilevel);
}
static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
--
2.34.1
- [PATCH v13 04/24] target/arm: Implement ALLINT MSR (immediate), (continued)
- [PATCH v13 04/24] target/arm: Implement ALLINT MSR (immediate), Jinjie Ruan, 2024/04/07
- [PATCH v13 03/24] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/04/07
- [PATCH v13 05/24] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/04/07
- [PATCH v13 08/24] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, Jinjie Ruan, 2024/04/07
- [PATCH v13 07/24] target/arm: Add support for NMI in arm_phys_excp_target_el(), Jinjie Ruan, 2024/04/07
- [PATCH v13 06/24] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/04/07
- [PATCH v13 09/24] target/arm: Handle PSTATE.ALLINT on taking an exception, Jinjie Ruan, 2024/04/07
- [PATCH v13 10/24] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/04/07
- [PATCH v13 13/24] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, Jinjie Ruan, 2024/04/07
- [PATCH v13 14/24] hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3, Jinjie Ruan, 2024/04/07
- [PATCH v13 22/24] hw/intc/arm_gicv3: Report the VINMI interrupt,
Jinjie Ruan <=
- [PATCH v13 20/24] hw/intc/arm_gicv3: Implement NMI interrupt priority, Jinjie Ruan, 2024/04/07
- [PATCH v13 11/24] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Jinjie Ruan, 2024/04/07
- [PATCH v13 21/24] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Jinjie Ruan, 2024/04/07
- [PATCH v13 15/24] hw/intc/arm_gicv3: Add irq non-maskable property, Jinjie Ruan, 2024/04/07
- [PATCH v13 12/24] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/04/07
- [PATCH v13 23/24] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/04/07
- [PATCH v13 16/24] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/04/07
- [PATCH v13 18/24] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/04/07
- [PATCH v13 17/24] hw/intc/arm_gicv3: Implement GICD_INMIR, Jinjie Ruan, 2024/04/07
- [PATCH v13 19/24] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Jinjie Ruan, 2024/04/07