The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts.
Place this in its own field within ENV, as that will
make it easier to handle ALLINT set/clear.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Signed-off-by: Jinjie Ruan<ruanjinjie@huawei.com>
---
v3:
- Remove ALLINT dump in aarch64_cpu_dump_state().
- Update the commit message.
---
target/arm/cpu.h | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 63f31e0d98..f9646dbbfb 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -224,6 +224,7 @@ typedef struct CPUArchState {
* semantics as for AArch32, as described in the comments on each
field)
* nRW (also known as M[4]) is kept, inverted, in env->aarch64
* DAIF (exception masks) are kept in env->daif
+ * ALLINT (all IRQ or FIQ interrupts masks) are kept in env->allint
* BTYPE is kept in env->btype
* SM and ZA are kept in env->svcr
* all other bits are stored in their correct places in env->pstate
@@ -261,6 +262,7 @@ typedef struct CPUArchState {
uint32_t btype; /* BTI branch type. spsr[11:10]. */
uint64_t daif; /* exception masks, in the bits they are in PSTATE */
uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */
+ uint64_t allint; /* All IRQ or FIQ interrupt mask, in the bit in PSTATE */