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[RFC PATCH v3 18/21] hw/intc/arm_gicv3: Implement NMI interrupt prioirty
From: |
Jinjie Ruan |
Subject: |
[RFC PATCH v3 18/21] hw/intc/arm_gicv3: Implement NMI interrupt prioirty |
Date: |
Fri, 23 Feb 2024 10:32:18 +0000 |
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the pending irq is NMI in gicv3_redist_update_noirqset and
gicv3_update_noirqset. And In irqbetter(), only a non-NMI with the same
priority and a smaller interrupt number can be preempted but not NMI.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
v3:
- Add missing brace
---
hw/intc/arm_gicv3.c | 63 ++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 56 insertions(+), 7 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index 0b8f79a122..75999edd19 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -21,7 +21,7 @@
#include "hw/intc/arm_gicv3.h"
#include "gicv3_internal.h"
-static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
+static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool is_nmi)
{
/* Return true if this IRQ at this priority should take
* precedence over the current recorded highest priority
@@ -33,11 +33,21 @@ static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t
prio)
if (prio < cs->hppi.prio) {
return true;
}
+
+ /*
+ * Current highest prioirity pending interrupt is not a NMI
+ * and the new IRQ is a NMI with same priority.
+ */
+ if (prio == cs->hppi.prio && !cs->hppi.superprio && is_nmi) {
+ return true;
+ }
+
/* If multiple pending interrupts have the same priority then it is an
* IMPDEF choice which of them to signal to the CPU. We choose to
* signal the one with the lowest interrupt number.
*/
- if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
+ if (prio == cs->hppi.prio && !cs->hppi.superprio &&
+ !is_nmi && irq <= cs->hppi.irq) {
return true;
}
return false;
@@ -141,6 +151,8 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
uint8_t prio;
int i;
uint32_t pend;
+ bool is_nmi = 0;
+ uint32_t superprio = 0;
/* Find out which redistributor interrupts are eligible to be
* signaled to the CPU interface.
@@ -152,10 +164,27 @@ static void gicv3_redist_update_noirqset(GICv3CPUState
*cs)
if (!(pend & (1 << i))) {
continue;
}
- prio = cs->gicr_ipriorityr[i];
- if (irqbetter(cs, i, prio)) {
+ superprio = extract32(cs->gicr_isuperprio, i, 1);
+
+ /* NMI */
+ if (superprio) {
+ is_nmi = 1;
+
+ /* DS = 0 & Non-secure NMI */
+ if ((!(cs->gic->gicd_ctlr & GICD_CTLR_DS)) &&
+ extract32(cs->gicr_igroupr0, i, 1)) {
+ prio = 0x80;
+ } else {
+ prio = 0x0;
+ }
+ } else {
+ is_nmi = 0;
+ prio = cs->gicr_ipriorityr[i];
+ }
+ if (irqbetter(cs, i, prio, is_nmi)) {
cs->hppi.irq = i;
cs->hppi.prio = prio;
+ cs->hppi.superprio = is_nmi;
seenbetter = true;
}
}
@@ -168,7 +197,7 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
(cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) &&
(cs->hpplpi.prio != 0xff)) {
- if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+ if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio, false)) {
cs->hppi.irq = cs->hpplpi.irq;
cs->hppi.prio = cs->hpplpi.prio;
cs->hppi.grp = cs->hpplpi.grp;
@@ -212,7 +241,9 @@ static void gicv3_update_noirqset(GICv3State *s, int start,
int len)
{
int i;
uint8_t prio;
+ bool is_nmi = 0;
uint32_t pend = 0;
+ uint32_t superprio = 0;
assert(start >= GIC_INTERNAL);
assert(len > 0);
@@ -240,10 +271,28 @@ static void gicv3_update_noirqset(GICv3State *s, int
start, int len)
*/
continue;
}
- prio = s->gicd_ipriority[i];
- if (irqbetter(cs, i, prio)) {
+
+ superprio = *gic_bmp_ptr32(s->superprio, i);
+ /* NMI */
+ if (superprio & (1 << (i & 0x1f))) {
+ is_nmi = 1;
+
+ /* DS = 0 & Non-secure NMI */
+ if ((!(s->gicd_ctlr & GICD_CTLR_DS)) &&
+ gicv3_gicd_group_test(s, i)) {
+ prio = 0x80;
+ } else {
+ prio = 0x0;
+ }
+ } else {
+ is_nmi = 0;
+ prio = s->gicd_ipriority[i];
+ }
+
+ if (irqbetter(cs, i, prio, is_nmi)) {
cs->hppi.irq = i;
cs->hppi.prio = prio;
+ cs->hppi.superprio = is_nmi;
cs->seenbetter = true;
}
}
--
2.34.1
- [RFC PATCH v3 07/21] target/arm: Add support for NMI in arm_phys_excp_target_el(), (continued)
- [RFC PATCH v3 07/21] target/arm: Add support for NMI in arm_phys_excp_target_el(), Jinjie Ruan, 2024/02/23
- [RFC PATCH v3 08/21] target/arm: Handle IS/FS in ISR_EL1 for NMI, Jinjie Ruan, 2024/02/23
- [RFC PATCH v3 02/21] target/arm: Add PSTATE.ALLINT, Jinjie Ruan, 2024/02/23
- [RFC PATCH v3 20/21] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/02/23
- [RFC PATCH v3 06/21] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/02/23
- [RFC PATCH v3 18/21] hw/intc/arm_gicv3: Implement NMI interrupt prioirty,
Jinjie Ruan <=
- [RFC PATCH v3 21/21] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC, Jinjie Ruan, 2024/02/23
- [RFC PATCH v3 17/21] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/02/23
- [RFC PATCH v3 03/21] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/02/23
- [RFC PATCH v3 05/21] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/02/23