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[Qemu-arm] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR |
Date: |
Fri, 29 Sep 2017 22:08:22 -0400 |
Also fix the existing bitmask for writes.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 54070a3..fcc2fcf 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1059,10 +1059,25 @@ static void pmccfiltr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
uint64_t value)
{
pmccntr_sync(env);
- env->cp15.pmccfiltr_el0 = value & 0x7E000000;
+ env->cp15.pmccfiltr_el0 = value & 0xfc000000;
pmccntr_sync(env);
}
+static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ pmccntr_sync(env);
+ env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & 0x04000000) |
+ (value & 0xf8000000); /* M is not visible in AArch32 */
+ pmccntr_sync(env);
+}
+
+static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ /* M is not visible in AArch32 */
+ return env->cp15.pmccfiltr_el0 & 0xf8000000;
+}
+
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1280,6 +1295,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.type = ARM_CP_IO,
.readfn = pmccntr_read, .writefn = pmccntr_write, },
#endif
+ { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 =
7,
+ .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
+ .access = PL0_RW, .accessfn = pmreg_access,
+ .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.pmccfiltr_el0),
+ .resetvalue = 0, },
{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
.writefn = pmccfiltr_write,
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies,
Inc.\nQualcomm Technologies, Inc. is a member of the\nCode Aurora Forum, a
Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v2 00/13] More fully implement ARM PMUv3, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0], Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR,
Aaron Lindsay <=
- [Qemu-arm] [PATCH 07/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2017/09/29
- [Qemu-arm] [PATCH 13/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2017/09/29